Twenty licensable cores, from the RF datapath of a 5G radio to the converters, clocking and buses underneath it. Silicon-proven where it counts, delivered as RTL against your FPGA or ASIC target, with the integration support to land it.
Faststream licenses the building blocks, not just the finished chip. These are cores we have designed, verified and in most cases proven in silicon — the kind of block that is expensive to get right from scratch and easy to get subtly wrong. Drop one into your SoC or FPGA and you buy back schedule and risk at the same time.
The range spans the whole datapath of a connected product: the RF and fronthaul blocks behind a 5G radio, the DSP and compute slices, the data converters, clocking and on-die monitors, the bus and timing interfaces that tie it all together, and the verification collateral that keeps integration honest.
Crest-factor reduction — lowers PAPR ahead of the power amplifier.
IP COREDigital predistortion — linearises the power amplifier.
IP COREFronthaul packetisation for the O-RAN 7.2x split.
IP COREFIR, decimation and interpolation filter chains.
IP COREEfficient multi-channel filtering and channelisation.
IP CORELow-PHY datapath for a 7.2x radio unit.
Analog-to-digital conversion IP.
IP COREDigital interface to industry-standard ADCs.
IP COREProcess, voltage and temperature monitoring.
IP COREPLL and clock generation.
IP COREEnergy-efficient, low-area serialiser / deserialiser.
USB 2.0 device controller with an AXI interface.
IP COREIEEE 1588 timing, with an automotive-Ethernet variant.
IP COREProtocol bridging between Ethernet, CAN and ALDL.
IP COREMemory interface and I/O library.
IP COREConfigurable synchronous serial engine, multiple protocols.
Every core comes as synthesisable RTL with a testbench, documentation and integration support, and is delivered against your target — a specific FPGA family or an ASIC process node. Where a block is silicon-proven we say so for the configuration you need; where it is FPGA-validated or at RTL stage, we say that too, rather than claiming maturity generically.
Licensing is straightforward: tell us the target, the interfaces and the performance you need, and we scope the core, the configuration and the support around your programme. If a block needs adapting — a wider datapath, a different bus, a tighter area or power budget — that is engineering we do rather than a reason to say no.
Twenty-plus synthesisable cores across wireless & RAN (CFR, DPD, eCPRI, digital filters, channelizer, O-RAN radio-unit low-PHY), digital & DSP, analog & mixed-signal (ADC, SerDes, PLL/clocking, PVT sensors), interfaces (USB, PTP, memory, serial, protocol bridges) and verification IP.
Many of the cores are silicon-proven; others are FPGA-validated or at RTL stage. We confirm the maturity for the specific configuration you need at enquiry rather than claiming it generically.
Primarily synthesisable RTL with a testbench, documentation and integration support, delivered against your FPGA family or ASIC process node. Hard-macro or layout deliverables are scoped per engagement where relevant.
Yes. A wider datapath, a different bus interface, or a tighter area or power budget is engineering we do. Tell us the target and constraints and we scope the configuration and support around them.
Give us the FPGA family or process node, the performance and the bus, and we will scope the core, the configuration and the support around your programme.