Full custom silicon from architecture through tapeout: partitioning, RTL, verification, design for test, synthesis, static timing analysis, physical implementation and production transition. Programmes run across mature and advanced nodes, with the node chosen by what the application needs rather than by which number is smallest.
Written before parts return. Which tests, in which order, with which equipment, and what each failure would indicate.
First power-on, interface validation, and the systematic isolation of anything that does not behave as simulated.
Performance across voltage, temperature and process corners, measured rather than inferred from the sign-off corners.
Production test development, coverage assessment and correlation between bench and tester results.
Failure mode analysis and the design or process changes that follow from it.
Reliability and qualification support appropriate to the target market and its service life.
Architecture and specification, RTL design, functional verification, design for test, synthesis, static timing analysis, physical implementation and tapeout, continuing into bring-up, characterisation, test program development and yield analysis.
No. Node selection is driven by the application. Mature nodes from 180 nm to 90 nm remain correct for secure identity, analog and mixed-signal and long-lifecycle industrial parts, largely because of embedded non-volatile memory options, analog performance and supply horizon.
Yes. A structured assessment of the existing RTL, constraints, verification state and physical progress comes first, so the handover starts from what is actually true rather than what the last status report said.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.