Faststream Silicon covers the full custom-chip path: architecture, RTL, verification, DFT, static timing analysis, physical implementation, mixed-signal integration and production transition. It runs across mature and advanced process nodes, chosen by what the application needs rather than by generation — 180 nm for a secure element with embedded non-volatile memory is the right answer as often as 16 nm is for a networking SoC.
Advanced does not mean appropriate. Analog content, embedded non-volatile memory, qualification burden, lifecycle and cost all push in different directions.
| Band | Typical applications | Why this band |
|---|---|---|
| 180–90 nm | Smart cards, secure identity, analog and mixed-signal, embedded NVM, long-lifecycle industrial | Mature NVM options, strong analog performance, low mask cost, long supply horizon |
| 65–40 nm | Secure microcontrollers, communications SoCs, integrated embedded systems | Balance of density and analog capability, wide IP availability |
| 28 nm and below | High-performance communications, networking, AI and compute-heavy SoCs | Density and power efficiency justify the mask and design cost |
Specific foundry and node experience is discussed under NDA. Public material describes capability rather than naming a foundry.
Requirements captured, partitioning agreed, power, area and performance budgets set, IP and node selected, risks named early rather than discovered at signoff.
Design and testbench developed in parallel. Coverage tracked from the first week, not assembled at the end.
Test structures inserted and validated. Synthesis constraints developed against the real timing intent.
Floorplan, place and route, clock tree, closure across corners and modes, signoff on timing, power integrity and physical verification.
Handoff package assembled, mask release supported, silicon bring-up and characterisation planned before parts return.
Test program, yield analysis, qualification support and long-term lifecycle engineering.
No. Node selection is driven by the application. Mature nodes from 180 nm to 90 nm remain the correct choice for smart cards, secure identity, analog and mixed-signal parts and long-lifecycle industrial products, largely because of embedded non-volatile memory options, analog performance and supply horizon.
Yes. Programmes are run from architecture through RTL, verification, DFT, timing closure, physical implementation and tapeout handoff, and continue into bring-up, characterisation and production transition.
Yes. The semiconductor IP catalogue includes Precision Time Protocol, data acquisition control, DSP slice, AXI USB 2.0 and other cores, licensed with verification collateral and integration support.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.