What does a SERDES do?
It converts wide parallel data into a high-rate serial stream for transmission and reconstructs the parallel data at the receiver, which is how chips communicate at rates where a parallel bus would be impractical.
PRODUCT · FAMILY 01
SERDES
An energy-efficient, low-area serialiser and deserialiser for high-speed links. SERDES is where a large share of an SoC's power budget goes in networking and data centre parts, which is why efficiency per lane is the specification that matters rather than peak rate alone.
WHAT IT IS
The short version.
A serialiser and deserialiser converts wide parallel data to a high-rate serial stream and back, which is how chips talk to each other at rates where a parallel bus would be impractical. In a networking or data centre SoC there may be dozens of lanes, and their aggregate power is a substantial fraction of the device budget.
That makes energy per bit the figure that decides system viability, not the headline rate. A lane that runs fast and hot constrains how many lanes the package and the thermal design can support, which in turn constrains the switch or interface bandwidth the product can offer.
Area matters for the same reason. Lanes are replicated, so per-lane area multiplies directly into die cost.
DETAIL
Characteristics
| Parameter | Detail |
|---|---|
| Function | Serialiser and deserialiser for high-speed serial links |
| Design emphasis | Energy efficiency and low area per lane |
| Replication | Intended for multi-lane instantiation |
| Node | Configured to the target process |
| Typical markets | Data centre, networking, high-speed interconnect |
Maturity — silicon-proven, FPGA-validated or RTL stage — is confirmed at enquiry for the specific configuration you need, rather than claimed generically here.
APPLICATIONS
Where it is used.
- Networking SoCs — switch and router interface lanes.
- Data centre interconnect — chip-to-chip and chip-to-module links.
- Storage controllers — high-rate host and device interfaces.
- Backplane links — board-to-board communication in chassis systems.
- Instrumentation — high-rate data offload from acquisition front ends.
- FPGA-to-ASIC conversion — replacing FPGA hard transceivers with licensed SERDES.
WHAT YOU RECEIVE
Deliverables and support.
- SERDES IP configured to the target process and lane rate.
- Integration documentation covering placement, supply and reference clock requirements.
- Characterisation data appropriate to the configuration.
- Engineering support through integration and silicon bring-up.
Next step
Send the target node, the interface requirements and the integration context. If this is not the right fit, that will be said early rather than discovered at integration.
COMMON QUESTIONS
Questions asked before an evaluation.
Why does energy efficiency matter more than peak rate?
Because lanes are replicated. Aggregate SERDES power is a substantial fraction of a networking SoC's budget, and a lane that runs hot constrains how many lanes the package and thermal design can support.
Is SERDES relevant to FPGA-to-ASIC conversion?
Yes, and it is one of the standard conversion tasks. FPGA transceivers are hard IP inside the device, so converting to an ASIC requires licensed SERDES or a custom design in their place.
KEEP READING
Related work.
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