Can Faststream take a chip all the way to production?
Yes. Programmes run from architecture through tapeout and continue into bring-up, characterisation, test program development, yield analysis and long-term lifecycle support.
SOLUTION 01
Semiconductor
Custom silicon programmes run from architecture through RTL, verification, DFT, timing closure and physical implementation to tapeout and production. Faststream also licenses IP into other people's SoCs and converts proven FPGA designs into ASICs — which is often the cheaper route to the same destination.
THREE ROUTES
Not every problem needs a new chip.
Full custom programme
Architecture through tapeout for a part that does not exist. Right when volume, power or integration justify the design and mask cost.
FPGA-to-ASIC conversion
A proven FPGA design migrated to an ASIC for unit cost, power and volume. Lower risk, because the function is already validated in hardware.
IP licensing and integration
Existing cores dropped into your SoC with integration support, where the requirement is a block rather than a chip.
PROGRAMME
How a silicon programme runs.
01
Architecture and feasibility
Partitioning, interfaces, power, area and performance budgets, IP and node selection. Risks named here rather than discovered at signoff.
02
RTL and verification
Design and testbench in parallel, coverage tracked from the start, formal applied where it pays.
03
DFT and synthesis
Scan, compression, memory BIST and boundary scan inserted and validated. Constraints developed against real timing intent.
04
Physical implementation
Floorplan, place and route, clock tree, multi-corner multi-mode closure, IR and EM analysis, physical verification.
05
Tapeout
Handoff package assembled and reviewed, mask release supported.
06
Bring-up and production
Characterisation, test program development, yield analysis, qualification and lifecycle support.
NODE SELECTION
Chosen by application.
| Band | Applications | Why |
|---|---|---|
| 180–90 nm | Smart cards, secure identity, analog and mixed-signal, embedded NVM, long-lifecycle industrial | NVM options, analog performance, mask cost, supply horizon |
| 65–40 nm | Secure microcontrollers, communications SoCs, integrated embedded | Density and analog balance |
| 28 nm and below | High-performance communications, networking, AI and compute | Density and power efficiency |
WHERE THIS APPLIES
Industries this serves.
COMMON QUESTIONS
What engineers ask before they call.
Is FPGA-to-ASIC conversion cheaper than a new design?
Usually, and lower risk, because the function has already been validated in hardware. The work is in removing FPGA-specific dependencies, mapping to ASIC technology, proving equivalence and closing physical implementation.
Do you work with our chosen foundry?
Yes. Foundry and node experience is discussed under NDA; public material describes capability rather than naming a foundry.
KEEP READING
Related work.
BUILD WITH FASTSTREAM
Bring us the difficult part.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.