Above a few gigabits per second the interface stops being a connection and becomes a channel with a loss profile. The silicon is usually the easy part; the constraint is the trace, the connector, the via stack and the crosstalk from whatever runs beside it.
| Interface | Typical use | Dominant constraint |
|---|---|---|
| SerDes (generic) | Chip-to-chip, backplane, custom links | Channel insertion loss and equalisation reach |
| PCIe | Host to accelerator, storage, peripherals | Channel budget, reference clock jitter, protocol compliance |
| DDR / LPDDR | External memory | Timing skew, termination, and write and read levelling |
| Ethernet (SGMII to 100G+) | Networking and transport | Channel loss, PHY selection, timing distribution |
| JESD204 | Converter to logic in RF and instrumentation | Deterministic latency and multi-lane alignment |
| MIPI | Camera and display in embedded systems | Short-reach discipline and EMI |
| USB | Host connectivity and service interfaces | Compliance testing and connector reality |
A specification quotes a data rate. What determines whether a link works is the insertion loss between transmitter and receiver at the Nyquist frequency, and that is a property of the board, the connector and the vias rather than of the silicon.
So the sequence is: establish the channel first, then choose the interface and the equalisation strategy that can close over it. Doing this in the other order — selecting a rate and then discovering the channel cannot carry it — produces a board re-spin, and it is the most common high-speed failure.
The specific mechanisms are unglamorous and reliably fatal. A signal crossing a plane split has no adjacent return path, so its return current detours and the eye closes for no reason visible in the schematic. A via stub resonates. Decoupling placed by convention rather than against a plane impedance target produces a power delivery network that is fine at DC and resonant exactly where it matters.
Edge rate rather than clock frequency. Once rise times are short enough that trace length is a meaningful fraction of the wavelength, transmission-line behaviour dominates and impedance, return paths and length matching become design constraints rather than good practice.
Choosing a rate before characterising the channel. Insertion loss at the Nyquist frequency — a property of the stack-up, connector and route, not the silicon — decides which rates are candidates, and discovering that late means a board re-spin.
Because a high-speed signal crossing one has no adjacent return path, so the return current takes a long detour. The result is emissions, crosstalk and a closed eye, none of which is visible in the schematic.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.