Faststream Technologies licenses semiconductor IP cores for digital, analog and mixed-signal integration, supplied with the verification collateral and integration support needed to land them in a customer SoC. The catalogue spans timing, data acquisition, signal processing, interface and automotive protocol blocks, and is also listed publicly on Design & Reuse.
| Core | Function | Typical markets |
|---|---|---|
| Precision Time Protocol IP | IEEE 1588 timing, including a variant for automotive Ethernet | Telecom, automotive, industrial |
| Analog Data Acquisition Controller IP | Digital interface to industry-standard ADCs | Industrial, medical, instrumentation |
| Multi-Protocol Synchronous Serial Engine IP | Configurable synchronous serial engine covering multiple protocols | Industrial, embedded |
| 18-bit Pipeline DSP Slice IP Core | Pipelined DSP slice for signal-processing datapaths | Communications, radar, industrial |
| AXI USB 2.0 Device IP | USB 2.0 device controller with AXI interface | Consumer, industrial, embedded |
| ADC IP | Analog-to-digital conversion IP | Mixed-signal SoC |
| SERDES | Energy-efficient, low-area serialiser and deserialiser | Data centre, networking |
| PVT Sensors | Process, voltage and temperature monitoring | All SoC |
| Ultra-low-jitter Clocking | PLL and clock generation | Communications, data centre |
| Memory Interfaces and I/O | Memory interface and I/O library | All SoC |
| Posit-based Processor | Processor using posit arithmetic | AI, scientific compute |
| Ethernet CAN-to-ALDL Bridge | Protocol bridging between Ethernet, CAN and ALDL | Automotive |
| Ethernet Filters for Digital PID Control | Control-loop filtering for electromechanical actuators | Aerospace, industrial |
| Verification IP | Protocol verification collateral | All SoC programmes |
Maturity varies across the catalogue. Silicon-proven, FPGA-validated and RTL-stage status for a specific core is confirmed at enquiry.
IP is delivered against the node the application needs. Mature nodes are not a fallback; for analog content, embedded non-volatile memory and long lifecycle they are the correct answer.
| Band | Typical applications | Driver |
|---|---|---|
| 180–90 nm | Smart cards, secure identity, analog and mixed-signal, embedded NVM, long-lifecycle industrial | NVM availability, analog performance, mask cost, supply horizon |
| 65–40 nm | Secure microcontrollers, communications SoCs, integrated embedded | Density and analog balance, wide IP availability |
| 28 nm and below | High-performance communications, networking, AI and compute SoCs | Density and power efficiency |
Interface, performance, node and integration context established. If a core is not the right fit, that is said early.
Parameterisation agreed against the target — data widths, interface variants, clocking and power intent.
Core delivered in the agreed form with integration documentation and verification collateral.
Engineering support through integration, simulation and hardware bring-up.
Updates, issue resolution and long-term support for products with extended production lives.
The IP catalogue is published on Design & Reuse, the industry's SIP core directory, under both the silicon IP and verification IP listings. If you are evaluating cores across suppliers, that is a reasonable place to start a comparison.
Faststream Technologies has been supplying mixed-signal IP since 2008. The portfolio has grown out of production programmes rather than being assembled as a catalogue, which is why several of the cores are specific rather than generic — the Ethernet CAN-to-ALDL bridge and the PID control filters exist because a customer needed them in a shipping product.
The catalogue includes Precision Time Protocol IP with an automotive Ethernet variant, an analog data acquisition controller, a multi-protocol synchronous serial engine, an 18-bit pipeline DSP slice, AXI USB 2.0 device IP, ADC IP, SERDES, PVT sensors, ultra-low-jitter clocking, memory interfaces and I/O, a posit-based processor, an Ethernet CAN-to-ALDL bridge, PID control filters and verification IP.
Maturity varies by core. Some are silicon-proven in production parts, some are FPGA-validated, and some are at RTL. The status of a specific core is confirmed at enquiry rather than claimed generically.
IEEE 1588 Precision Time Protocol distributes accurate time across a network so that distributed nodes share a common clock. It is used in telecom transport, industrial control, test and measurement, and — via the automotive Ethernet variant — in vehicle networks where sensor data must be timestamped consistently.
Yes. IP integration, interface bring-up and integration verification are standard parts of a silicon programme, whether the cores are Faststream's, the customer's or a third party's.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.