Analog and RF are where most integration risk concentrates, because the failure modes are continuous rather than discrete. A digital block works or it does not. An analog block degrades — noise creeps up, a reference drifts with temperature, a supply couples into a sensitive node — and the symptom appears three levels away in a specification that will not close.
Analog blocks are rarely limited by the thing their name suggests. Knowing which parameter binds is most of the design.
| Block | What it does | What actually limits it |
|---|---|---|
| Bandgap reference | A voltage that does not move with temperature or supply | Start-up behaviour and device matching; a reference that will not start below the rail it enables is a common failure |
| Low-dropout regulator (LDO) | A clean rail for sensitive analog blocks | Stability across load and capacitor choice, and power supply rejection at the frequencies that matter |
| Phase-locked loop (PLL) | Clock generation and frequency synthesis | Phase noise, which is set by the oscillator and loop bandwidth long before the divider architecture matters |
| Data converter | The boundary between continuous and discrete | Sampling clock jitter at high input frequencies, and matching in the reference ladder or capacitor array |
| Comparator | A decision at a threshold | Offset, kickback into the sampled node, and metastability at the resolution boundary |
| Operational amplifier / OTA | A controlled gain stage for conditioning, feedback and driving the next block | Gain-bandwidth against stability and power, and input-referred offset and noise that no later stage can remove |
| Ring oscillator | A compact, process-friendly on-chip clock or on-die monitor | Jitter and strong supply and temperature sensitivity — the simplicity that makes it cheap is also what makes it move |
| SerDes / high-speed PHY | The electrical layer of a fast serial link | Channel loss and the jitter budget; equalisation and clock-and-data recovery decide whether the eye is still open at the far end |
| Temperature sensor | The die reporting its own operating point for calibration and protection | Accuracy after a one- or two-point trim, and self-heating of the sensor itself |
| Power management | Supply generation and sequencing | Efficiency across the whole load range rather than at the operating point on the datasheet |
Every one of these is verified across process, voltage and temperature corners and by statistical analysis, because a block that works at nominal and fails at three sigma has not been designed.
RF is a budget discipline. Noise, linearity and gain are allocated across the chain before any single block is designed. It is the same chain whether it feeds a 5G or O-RAN radio, a satellite terminal, an FMCW or mmWave radar, or a Wi-Fi, SDR or short-range link — the LNA that sets the noise figure and the PA that burns most of the transmit power are where a radio's reach, a radar's range and the battery life are decided.
| Block | Contribution | Design tension |
|---|---|---|
| Low-noise amplifier (LNA) | Sets the noise figure for everything after it | Noise figure against linearity and current; the first stage dominates, which is why it gets the power |
| Mixer | Frequency translation | Conversion gain against linearity and local oscillator leakage |
| Voltage-controlled oscillator (VCO) | The local oscillator the mixer needs | Phase noise against tuning range and power, with pulling from nearby switching a constant hazard |
| Filters | Selectivity before and after conversion | Insertion loss directly consumes noise figure, so selectivity is never free |
| Power amplifier (PA) | Transmit power | Efficiency rises toward saturation and linearity falls; this is the tension digital pre-distortion exists to relieve |
| Matching networks | Impedance transformation at every interface | Correct at one operating point; bandwidth and load variation move it away |
Transceiver architecture — direct conversion, low-IF or superheterodyne — is chosen against these tensions rather than by preference, and it fixes most of what follows.
Analog and mixed-signal performance is set as much in the layout as in the schematic, so we treat custom layout as a deliverable in its own right — taken on standalone, or as part of a full block design. Device-level, polygon by polygon, closed to foundry signoff.
Delivered as a DRC/LVS-clean GDSII with the extracted netlist and signoff reports, on nodes from mature analog processes to FinFET. On tools such as Cadence Virtuoso and Siemens Calibre.
A converter that meets specification on its own may not meet it beside a switching regulator on the same die. A PLL that is clean on the bench may not be clean when the digital logic beside it starts switching at full rate. A reference that is stable at 25 degrees may not be at 105.
Which is why analog integration is a floorplanning and partitioning discipline as much as a circuit one, and why post-layout verification across corners is not optional. The corners that matter are rarely the ones the schematic simulation was run at.
| Consideration | Mature nodes (180–90 nm) | Advanced nodes (28 nm and below) |
|---|---|---|
| Supply headroom | Ample; stacked topologies straightforward | Constrained; limits achievable dynamic range |
| Device matching | Well characterised and predictable | Requires more area to reach equivalent matching |
| Embedded non-volatile memory | Widely available | Limited or unavailable |
| Mask and design cost | Low | High |
| Supply horizon | Long, suiting decade-long products | Shorter generational cycle |
| Digital density | Limited | Excellent |
Which is why a part with significant analog content and a ten-year service life is frequently correct at 180 nm and would be worse at 16 nm.
Voltage and current references, regulators and power management, clocking and PLLs, data converters, comparators and the supporting circuitry these need — designed, verified across corners and statistically, and taken through post-layout to signoff.
Receive and transmit chains — low-noise amplifiers, mixers, oscillators, filters, matching and power amplifier integration — with the noise, linearity and gain budget allocated across the chain before individual blocks are designed. The same chain serves cellular, O-RAN and satellite radios and FMCW or mmWave radar.
Corner analysis catches systematic variation. Random mismatch between nominally identical devices is statistical, and it determines yield on matched pairs, converter arrays and reference circuits. A design verified only at corners can meet specification and still fail in volume.
Because its noise figure dominates the whole chain. Noise added early is amplified by everything after it; noise added late is not. That is why the low-noise amplifier receives the current budget and the design effort.
Because the failure modes are continuous and coupled. Supply noise from a neighbouring switching block, substrate coupling from digital switching, thermal gradients across the die and layout parasitics all shift analog performance in ways a standalone schematic simulation does not capture.
Supply headroom, device matching, embedded non-volatile memory availability, mask cost and supply horizon all favour mature nodes for analog-heavy parts. Advanced nodes win on digital density, which is a different problem.
Yes — transceiver integration, filtering, matching, antenna interface and link budget work, connected to the digital front end capability under the Radio platform.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.