FPGA-to-ASIC conversion migrates a design that already works in hardware into a production ASIC, for unit cost, power and volume. It is lower risk than a new design because the function is validated — but the FPGA-specific dependencies embedded throughout it are exactly what has to be removed, and finding all of them is the work.
The design is read rather than assumed: coding style, hierarchy, clock domains, memory usage, constraint quality and verification state. This produces the realistic effort estimate everything else depends on.
Vendor primitives, block RAM and distributed RAM inference, DSP block usage, transceiver hard IP, clock management tiles, I/O primitives and initialisation-on-configuration behaviour — all catalogued, because each needs an ASIC equivalent or a redesign.
FPGA clock management becomes PLLs. Inferred memories become compiled macros with different timing and test requirements. Reset strategy is revisited, because FPGA configuration provides a known initial state that ASIC flip-flops do not.
Hard IP with no ASIC equivalent is replaced with licensed cores or custom design, with interface and timing differences resolved rather than papered over.
The point of the conversion. FPGA-oriented structures are restructured for ASIC implementation, where the trade-offs are different in kind, not just in degree.
The converted design is proven functionally equivalent to the validated FPGA design, using the existing regression suite extended to cover what the changes touched.
Scan, compression, memory BIST and boundary scan inserted — a category of work with no FPGA counterpart at all, and frequently underestimated.
Floorplan, place and route, clock tree, multi-corner multi-mode closure, power integrity and physical verification.
Pinout, package selection, signal integrity and the board changes the new part implies.
Handoff, mask release, bring-up planning, test program development and yield analysis.
| Aspect | In the FPGA | In the ASIC |
|---|---|---|
| Initial state | Configuration sets every flip-flop at power-up | Explicit reset required; undefined state otherwise |
| Memory | Inferred block RAM with fixed behaviour | Compiled macros with different timing, power and test needs |
| Clock management | Clock management tiles and vendor primitives | PLLs designed or licensed, with their own lock and jitter behaviour |
| DSP resources | Hard DSP blocks with fixed structure | Synthesised arithmetic, optimisable to the actual precision needed |
| Transceivers | Hard IP in the device | Licensed SerDes IP or custom design |
| Test | Vendor infrastructure and readback | Full DFT insertion: scan, BIST, boundary scan, ATPG |
| Timing | Closure against a fixed fabric | Closure across process, voltage and temperature corners |
| Fixing a bug | Reconfigure | New mask set |
The last row is the reason verification equivalence is not a formality.
Conversion pays when annual volume multiplied by the per-unit FPGA cost premium exceeds the non-recurring engineering and mask cost over the product's life — with power and board area frequently mattering as much as the bill of materials.
It also pays where the FPGA itself is the supply risk: long lead times, allocation, or an end-of-life notice on a device the product depends on.
It does not pay where the function is still moving, where volume is genuinely low, or where the ability to update deployed units is a product requirement rather than a convenience. Those are cases to say no to, and saying so early is cheaper for everyone.
It is the migration of a design already implemented and validated on an FPGA into an application-specific integrated circuit, to reduce unit cost and power at volume. The work centres on removing FPGA-specific dependencies, mapping to ASIC technology, adding test structures, proving functional equivalence and closing physical implementation.
When annual volume times the per-unit FPGA cost premium exceeds the engineering and mask cost over the product life, when power or board area constraints cannot be met with an FPGA, or when the FPGA itself presents a supply or obsolescence risk. It does not make sense while the function is still changing or where field reconfigurability is a product requirement.
Through a combination of the existing FPGA regression suite extended to cover what the conversion touched, formal equivalence checking where the transformation permits it, and gate-level simulation. Because a post-tapeout bug costs a mask set, this stage is not compressed.
Design for test. FPGAs provide their own test infrastructure, so an FPGA design carries no scan chains, no memory BIST and no boundary scan. All of that has to be inserted, validated and delivered as production patterns, and it is real work with no FPGA counterpart.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.