Power is three separate problems wearing one name: dynamic switching, clock distribution and static leakage. They respond to different techniques, they dominate at different nodes, and a design that optimises the wrong one arrives at signoff having spent effort without moving the number that mattered.
| Component | Driver | Technique | Dominant when |
|---|---|---|---|
| Dynamic switching | Capacitance, voltage squared, switching activity | Activity reduction, operand isolation, lower supply | High-activity datapaths at any node |
| Clock distribution | Clock tree capacitance and toggle rate | Clock gating at every level of hierarchy | Almost always a top-two contributor |
| Static leakage | Threshold voltage, temperature, area | Multi-threshold cells, power gating, body bias | Below 28 nm, and at high temperature |
| Memory | Array leakage and access energy | Bank partitioning, retention modes, access reduction | Memory-heavy designs |
| I/O | Drive strength and off-chip capacitance | Interface selection, termination discipline | High-pin-count parts |
Clock power is the one most often underestimated, because it is distributed and therefore does not appear as a line item next to any block.
Power intent described in comments and reviews gets implemented differently by synthesis, place-and-route and verification. Described in UPF, it is a single source that every tool reads — which is the only way a multi-domain design closes without a class of bug that only appears at a domain boundary.
At mature nodes leakage is small and dynamic power dominates, so effort goes into activity reduction and clock gating. Power gating buys little and costs area and complexity.
Below 28 nm leakage becomes a first-order contributor, particularly at temperature, and a part that idles for most of its duty cycle can burn most of its energy doing nothing. Power gating and multi-threshold libraries stop being refinements and become the primary technique.
This is one of several reasons node selection is an architecture decision rather than a procurement one. A long-lifecycle industrial part that spends its life idling may well use less energy at 90 nm than at 16 nm, which is the opposite of the intuition.
The Unified Power Format, a file describing power intent — domains, isolation, retention, level shifting, legal power states and sequencing — that synthesis, place-and-route and verification all read, so a multi-domain design is implemented consistently.
It depends on the node and the duty cycle. At mature nodes dynamic dominates. Below 28 nm leakage becomes first-order, especially at temperature, and a part that idles most of the time can spend most of its energy doing nothing.
Because the clock tree is distributed rather than being a block, so it does not appear as a line item next to anything. It is frequently one of the two largest dynamic contributors, which makes hierarchical clock gating one of the highest-return techniques available.
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