RTL to GDSII is the path from a synthesisable hardware description to the polygon database a foundry manufactures from. Fifteen stages, each with its own signoff, and a discipline that matters more than any single tool: a stage is not complete because it ran, but because what it was supposed to prove has been proven.
Function, interfaces, throughput, latency, power and area budgets fixed. Every later decision is held against these numbers, and a programme without them cannot tell whether it is on track.
Synthesisable Verilog or SystemVerilog with the clock and reset architecture designed rather than accumulated. Lint and clock-domain-crossing analysis clean as a condition of check-in, not a later cleanup phase.
UVM environment, constrained-random stimulus, coverage model derived from the specification. Runs in parallel with design, not after it.
Scan chains stitched, compression configured, memory BIST inserted, boundary scan added. Done before synthesis signoff because test structures change timing and area materially.
RTL mapped to the standard-cell library under timing, area and power constraints. Output is a gate-level netlist plus the constraint set the back end inherits.
The netlist proven logically equivalent to the RTL. Cheap to run, and the only defence against a synthesis or optimisation step having changed behaviour.
Die size, macro placement, power grid, pin assignment and blockages. The single most consequential stage: a poor floorplan makes timing closure difficult and sometimes impossible, and no downstream tool recovers it.
Rings, straps and via stacks sized against the current the design will actually draw, with electromigration limits respected rather than assumed.
Cells positioned for timing and congestion. Legalisation, scan reordering and useful-skew opportunities all resolved here.
The clock distributed with skew, latency and insertion delay managed across every mode and corner. Clock power is frequently the largest single dynamic contributor, so this stage is a power decision as much as a timing one.
Global then detailed routing, with congestion, crosstalk, antenna rules and double-patterning constraints where the node imposes them.
Resistance and capacitance extracted from the routed geometry, producing the annotated data timing analysis actually depends on.
Multi-corner multi-mode closure against extracted parasitics. Setup, hold, transition, capacitance and clock-gating checks, with every exception documented and justified.
Static and dynamic IR drop against real switching activity, electromigration on signal and power nets, and thermal behaviour at the intended operating point.
Design rule check, layout versus schematic, antenna, density and metal-fill. A clean signoff, then the GDSII handoff package assembled and reviewed before mask release.
Programmes get into trouble by assuming one check covers what another does. It does not.
| Check | Proves | Does not prove |
|---|---|---|
| Lint and CDC | Coding and clock-crossing hygiene | That the function is correct |
| Functional verification | The design does what the specification says | That the netlist matches the RTL |
| Formal equivalence | Netlist and RTL are logically equivalent | That timing closes |
| Static timing analysis | Paths meet timing across corners and modes | That reset and initialisation behave, or that async interfaces are safe |
| Gate-level simulation | Reset sequencing, X-propagation and initialisation behaviour | Coverage of the functional space |
| IR drop analysis | Supply integrity under the modelled switching activity | Behaviour under activity patterns that were not modelled |
| DRC and LVS | The layout is manufacturable and matches the netlist | Anything at all about timing or function |
| ATPG coverage | Manufacturing defects are detectable | That the design is functionally correct |
The fifth row is the one most often skipped under schedule pressure. Static timing analysis cannot see a reset that never releases, and that class of bug costs a mask set.
It is the digital implementation flow from a synthesisable register-transfer-level hardware description to the GDSII polygon database a foundry manufactures from. It spans synthesis, DFT insertion, floorplanning, placement, clock tree synthesis, routing, extraction, timing closure, power integrity and physical verification.
Floorplanning. It fixes die size, macro placement and the power grid, and a poor floorplan makes timing closure difficult or impossible in ways no downstream tool recovers. It is also the stage under most pressure to be settled before enough is known.
Because they prove different things. Timing analysis confirms paths meet timing; it cannot see a reset that never releases, X-propagation through uninitialised logic, or unsafe asynchronous interface behaviour. That class of bug survives timing signoff and costs a mask set.
Proving the synthesised netlist is logically equivalent to the RTL. It is inexpensive and it is the only systematic defence against a synthesis or optimisation step having silently changed behaviour.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.