Advanced does not mean appropriate. For parts with significant analog content, embedded non-volatile memory or a decade-long service life, a mature node is frequently the correct engineering answer rather than a compromise — and treating node selection as a race to the smallest number produces worse silicon at higher cost.
| Consideration | 180–90 nm | 65–40 nm | 28 nm and below |
|---|---|---|---|
| Supply headroom | Ample | Moderate | Constrained |
| Device matching | Predictable, well characterised | Good | Requires more area for equivalent matching |
| Embedded NVM | Widely available | Available | Limited or unavailable |
| Digital density | Limited | Good | Excellent |
| Leakage | Low | Moderate | Requires active management |
| Mask cost | Low | Moderate | High |
| Supply horizon | Long | Long | Shorter generational cycle |
| Typical fit | Smart cards, secure identity, analog, industrial | Secure MCU, comms SoC | Networking, AI, high-performance comms |
Analog performance depends on supply headroom, device matching and predictable behaviour, and all three degrade as geometry shrinks. Lower supply voltages constrain the dynamic range achievable from stacked topologies. Matching worsens with device size, so equivalent precision costs proportionally more area at an advanced node than at a mature one.
Embedded non-volatile memory is the other decisive factor. Smart cards, secure elements and many industrial controllers need on-die NVM, and the process options for it thin out sharply below about 40 nm.
Then there is time. A product with a ten-year service life needs a node that will still be in production near the end of it. Mature nodes have long supply horizons; leading-edge nodes are generational.
Because supply headroom, device matching, embedded non-volatile memory availability, low mask cost and a long supply horizon all favour it for parts with significant analog content or a decade-long service life. Smart cards, secure elements and many industrial controllers are correct at 180 nm and would be worse at an advanced node.
When digital density and power efficiency are the binding constraints — high-performance communications, networking, AI and compute-heavy SoCs — and volume amortises the substantially higher mask and design cost.
Considerably. The cores a design depends on have to exist, be silicon-proven and be licensable on the chosen node, and that availability sometimes decides the node rather than the other way round.
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