A silicon programme runs inside an environment, and the environment is frequently what determines whether it finishes on time. Process design kits, standard-cell and memory libraries, IP availability on the chosen node, EDA licences and a reproducible flow — each of these is a dependency that can stop a programme dead.
Faststream works with TSMC and GlobalFoundries process design kits across mature and advanced nodes. Which specific node a programme uses is decided against the application and confirmed at enquiry, because availability, IP and schedule move.
| Foundry | Where it typically suits | What that means in practice |
|---|---|---|
| TSMC | Digital-led designs where density, speed or leakage decide the outcome | Advanced-node flows, wide third-party IP availability, and the tool and library maturity that comes with a large ecosystem |
| GlobalFoundries | Analog-heavy, RF and long-lifecycle parts | Mature and specialty processes with embedded non-volatile memory, analog headroom and a supply horizon that suits a decade-long product |
| Node range worked across | 180 nm through sub-28 nm | Chosen by what the application needs rather than by which number is smallest — see process node selection |
Faststream is a design company, not a foundry. Access to a PDK is not the same as a manufacturing commitment, and wafer supply is contracted between the customer and the foundry unless agreed otherwise.
A design needs a SerDes, a PLL, embedded non-volatile memory and a USB physical layer. Each has to exist on the chosen node, be silicon-proven there, and be licensable within the schedule and budget. If one is not, the options are a different node, a custom design, or a specification change.
This is why IP availability belongs in the node decision rather than downstream of it, and why the availability question is asked early enough that the answer can still influence anything. Discovering at month five that the required NVM is not offered below 40 nm is an expensive way to learn the node was wrong.
Silicon programmes run for a year or more and are revisited for years after. A timing report that cannot be regenerated — because the script was interactive, the tool version moved, or the input data was not versioned — is an assertion rather than evidence.
So the flow is scripted, the tool versions are pinned, the inputs are under version control, and the results are archived with enough context to be reproduced. This matters most at exactly the moment it is least convenient: when a field failure prompts someone to ask what the signoff actually said.
TSMC and GlobalFoundries process design kits, across mature and advanced nodes. Which foundry and node a programme uses is decided against the application — density and speed favour one set of choices, analog headroom, embedded non-volatile memory and a long supply horizon favour another.
No. Faststream is a design company. It works within the foundry's PDK and delivers a signed-off tapeout package; wafer supply is contracted between the customer and the foundry unless a programme is structured otherwise.
The foundry-supplied collection of device models, design rules, technology files and verification decks a design must be built against. A programme is tied to a specific PDK revision, and moving revision mid-programme is a managed change rather than an upgrade.
Because the cores a design depends on — SerDes, PLLs, embedded non-volatile memory, interface physical layers — must exist on that node, be silicon-proven there and be licensable within the schedule. If one is not available, the node has to change or the design does.
Because a field failure prompts someone to ask what signoff actually said. A timing report that cannot be regenerated is an assertion, not evidence — which is why scripts, tool versions and inputs are all versioned and archived.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.