Design for test adds circuitry whose only purpose is to make manufacturing defects detectable. It costs area, timing margin and design effort, and without it a foundry cannot tell you which die work — which means every part shipped is a hope rather than a measurement.
| Structure | Detects | Cost |
|---|---|---|
| Scan chains | Stuck-at and transition faults in combinational and sequential logic | Area for scan flops, plus routing and a timing mode to close |
| Test compression | Same coverage with far fewer patterns | Decompressor and compactor logic; modest area |
| Memory BIST | Faults inside RAM arrays, which scan cannot reach | Controller area per memory group |
| Boundary scan (JTAG) | Board-level interconnect faults after assembly | I/O cell area and a test access port |
| Analog and mixed-signal test | Parametric behaviour of converters, PLLs and references | Test structures and significant tester time |
| On-chip monitors | Process corner, voltage and temperature at test and in the field | Small; the payback is disproportionate |
Test coverage is frequently discussed qualitatively, which is how a product reaches volume with a class of defect nobody detects. Stating it explicitly — which fault models, at what coverage, on which blocks — turns an assumption into an engineering decision with a cost attached.
The trade is visible once stated. Higher coverage costs pattern count, tester time and sometimes area; lower coverage costs field returns. Which is preferable depends on unit value, warranty exposure and how expensive a field failure is, and that is a business decision that should be made with numbers in front of it.
For automotive and safety-relevant parts the decision is partly made for you, because a diagnostic coverage figure is an input to the safety case rather than a commercial preference.
Written before tapeout. Which tests, in which order, with which equipment, and what each possible failure would indicate. A plan written after parts arrive is improvisation on the most expensive hardware in the building.
Supply sequencing, current draw against expectation, clock presence, basic liveness. Most first-silicon problems are found and understood here.
Each external interface exercised, characterised and correlated against simulation.
Performance across voltage, temperature and process corners, measured rather than inferred from the signoff corners.
Production patterns brought up on the tester, with bench and tester results correlated before volume.
Failure modes classified by cause, with the design or process change that follows from each.
Verification proves the design is correct. DFT proves a manufactured instance of it has no fabrication defects. They answer different questions, and without the second a foundry cannot tell you which die work.
It depends on unit value, warranty exposure and the cost of a field failure — and for automotive or safety-relevant parts, on the diagnostic coverage the safety case requires. The important thing is that the number is stated and chosen rather than inherited.
Because an FPGA provides its own test infrastructure, so an FPGA design contains no scan chains, no memory BIST and no boundary scan. All of it has to be inserted, validated and delivered as production patterns, and it is the most commonly underestimated line in a conversion estimate.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.