Dependency removal, reset architecture, DFT insertion and verification equivalence through to tapeout. The function was never in doubt; the work was in the assumptions the FPGA had been quietly satisfying.
The customer had a design working in the field on an FPGA, with volume rising to the point where the per-unit cost premium and the power consumption both mattered. The function was stable; the economics had changed.
That is the ideal case for conversion, and it is still not a translation exercise. An FPGA design carries assumptions that are invisible until removed: every flip-flop is initialised by configuration at power-up, memories are inferred with fixed behaviour, clock management is a vendor primitive, transceivers are hard IP, and there is no test infrastructure at all because the device provides its own.
Each of those has to be found, given an ASIC equivalent, and proven not to have changed the function — because after tapeout, a bug costs a mask set rather than a rebuild.
Stated as the customer stated them, before any of them had an answer. A challenge that is only described after it was solved is a description of the solution.
FPGA-specific behaviour is distributed through the design rather than isolated. Finding all of it is the work; missing one is a mask set.
Configuration sets every flip-flop at power-up. An ASIC does not. Adding correct reset without changing behaviour touches the entire design.
An FPGA provides its own. The converted design needed scan, compression, memory BIST and boundary scan inserted from nothing — with no counterpart in the source to estimate from.
The customer's confidence rested on the design still doing exactly what the validated FPGA version did. Verification effort was weighted toward proving that rather than exploring new behaviour.
The three blocks marked in the Convert row are where the effort actually goes, and the Add row has no counterpart in the source design at all — which is why DFT is the most commonly underestimated line in a conversion estimate.
The specific scope, rather than a capability list. Where a stage was shared with the customer’s team, it is described as shared.
Rarely the subsystem that sounds difficult. Written out because a reader facing the same programme gets more from this than from a summary of what went well.
The FPGA relied on configuration to set every flip-flop; the ASIC does not. Adding correct reset without changing behaviour touches the entire design and is routinely under-scoped in conversion estimates.
An FPGA design contains no scan chains, no BIST and no boundary scan, so none of that work appears in the code being converted. It is nonetheless a substantial part of the programme.
Inferred FPGA memories and compiled ASIC macros differ in read-during-write behaviour, latency and initialisation. Each difference is a potential functional change that has to be found deliberately.
Because a post-tapeout bug costs a mask set, verification effort went into proving the design still did what it already did, rather than into exploring behaviour nobody had asked for.
The converted design went through DFT, physical implementation and signoff to tapeout with functional equivalence demonstrated.
The economics that motivated the conversion — per-unit premium and power at volume — were the design targets throughout.
The dependency catalogue and effort model from the assessment stage is reusable, which makes the next conversion cheaper to scope.
Conversion is attractive because the function is already validated, and non-trivial because the FPGA had been quietly satisfying assumptions nobody had written down.
Customer projects are presented at property, capability, outcome and integration level. Customer names, internal architecture, register maps, state machines and confidential deliverables are not disclosed. Where a figure would identify a customer or a design, it is omitted rather than approximated. More detail is available under a non-disclosure agreement, within the limits each customer has agreed.
Every item links to its own page, with characteristics, applications and the maturity status stated honestly for that item.
The ten-stage process in full.
KNOWLEDGEWhen conversion pays, and when it does not.
TECHNOLOGYThe work with no FPGA counterpart.
TECHNOLOGYHow equivalence was proven.
PRODUCTReplacing FPGA hard transceivers.
PRODUCTReplacing FPGA I/O primitives.
Reset architecture and design for test. FPGAs initialise every flip-flop through configuration and provide their own test infrastructure, so neither appears in the design being converted — yet both are substantial work in the ASIC.
Through the existing FPGA regression extended to cover the changed areas, formal equivalence checking where the transformation permits it, and gate-level simulation. Because a post-tapeout bug costs a mask set, this stage is not compressed.
When annual volume times the per-unit FPGA cost premium exceeds engineering and mask cost over the product life, or when power, board area or FPGA supply risk cannot be resolved any other way.
A dependency catalogue, a scope, an effort estimate and a recommendation — including, where it applies, a recommendation not to proceed.
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