Conversion pays when annual volume multiplied by the per-unit FPGA cost premium exceeds non-recurring engineering and mask cost over the product's life. That is the headline arithmetic, and it is incomplete — power, board area, supply risk and the value of field reconfigurability all enter the calculation, sometimes decisively.
These are directional. A specific decision needs the actual numbers, and the assessment exists to produce them.
| Signal | Points toward |
|---|---|
| High and sustained annual volume | Conversion — the premium compounds |
| Function stable for 12 months or more | Conversion — the bet is small |
| Power budget not achievable on FPGA | Conversion — a feasibility issue, not an economic one |
| FPGA on allocation or end-of-life notice | Conversion — supply risk dominates |
| Requirements still moving | Stay on FPGA |
| Field reconfigurability is a product feature | Stay on FPGA |
| Low volume with modest premium | Stay on FPGA |
| Market window shorter than a silicon cycle | Stay on FPGA |
Design for test. An FPGA design contains no scan chains, no memory BIST and no boundary scan, because the device provides its own test infrastructure. All of it has to be inserted, validated and delivered as production patterns. It is real work with no counterpart in the source design, and it is the most commonly omitted line item.
Reset architecture. FPGA configuration sets every flip-flop at power-up. An ASIC does not. Adding correct reset without changing behaviour touches the whole design.
Verification equivalence. Because a post-tapeout bug costs a mask set, proving the converted design does exactly what the validated one did carries more weight than typical verification. That effort is not optional and not small.
Memory behaviour. Inferred FPGA memories and compiled ASIC macros differ in read-during-write semantics, latency and initialisation. Each difference is a potential functional change that has to be found deliberately.
Compare annual volume multiplied by the per-unit cost premium against total non-recurring engineering plus mask cost across the product life, then adjust for power, board area and supply risk — any of which can make the decision independently of unit cost.
Then stay on FPGA. Conversion fixes the function in silicon, and a mask set is an expensive way to discover that a specification moved.
Less risky, generally, because the function has already been validated in hardware. The risk shifts to finding every FPGA-specific dependency, which is what the assessment stage exists to catalogue.
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