A mining chip is not a fast computer; it is a machine for converting joules into hashes at the lowest possible cost. Everything that matters — competitiveness, margin, whether the design is obsolete before it ships — is set by decisions made in the micro-architecture, the power delivery and the floorplan, not by the algorithm, which is fixed and public.
The algorithm is public and fixed. There is no cleverness to hide in it, and no feature list to compete on. A mining ASIC competes on exactly two figures — energy per hash and cost per hash — and a design that is a few per cent worse on either is not slightly behind; it is unshippable.
That reframes the whole exercise. The hash function is implemented once as a deeply pipelined core, tuned for the shortest path and the least energy per round. Then the real engineering begins: replicating that core as many times as the reticle, the power budget and the thermal envelope will allow, and feeding every copy without the clock tree, the power delivery or the heat becoming the thing that limits throughput. The core is a solved problem; the array is where the money is.
The case for programmable logic is flexibility — and a mining workload has none to exploit. The function is frozen, so every transistor a CPU, GPU or FPGA spends on generality is spent on energy per hash that a fixed-function ASIC simply does not pay.
That is the textbook case for an ASIC, and mining is close to its purest example: enormous volume of a single, unchanging computation, where the only axes of competition are efficiency and cost. It is also a discipline in honesty about obsolescence — difficulty rises and price moves, so a design has to be right the first time and amortise quickly, which puts the weight back on getting the micro-architecture, the power and the floorplan right before tapeout rather than after.
Both work, and both lose on energy per hash at scale because they carry generality the workload cannot use. An FPGA is the right tool for prototyping and low volume; at volume, a fixed-function ASIC is several times more efficient, and efficiency is the whole competition.
Power and heat, well before logic area. The die can usually hold more cores than the power delivery and the thermal envelope can sustain, so the design is balanced to the wattage the package and board can actually remove.
Often, because energy per hash improves with node — but not blindly. Mask cost, yield on a large die and time-to-tapeout against a rising difficulty curve all push back, and the right node is the one that wins on cost per hash over the chip’s useful life, not on paper efficiency.
The building blocks are the same — RTL, physical implementation, clocking, power, DFT, mixed-signal — but the objective function is unusually pure. There is one number to beat, multiplied by millions of copies, which makes small per-core decisions matter more than almost anywhere else in silicon.
Written for engineers. Share it with one.
A fixed function, multiplied to the reticle, with energy and cost per operation as the only scores. If that is the shape of your problem, it is the shape we work in.