A chip is tested once, on a tester, through its pins, before it ships. Then it goes into a car, a pacemaker or a factory robot and runs for ten or fifteen years with no tester in sight. Built-in self-test is how the part keeps checking itself after the tester is long gone — and for anything safety-critical, that second life is the whole point.
Automated test equipment is extraordinary and expensive, and it is only ever in one place: the factory. It applies carefully generated patterns through the device pins, measures the responses, and decides whether the part is good. For a chip that will live its whole life in a sealed consumer gadget, that single verdict is enough.
It is not enough for a brake controller. A fault that was not present at manufacture — a memory cell that weakens, a transistor that degrades, a bond that cracks under thermal cycling — appears years later, in the field, with no tester anywhere near it. If nothing on the chip is capable of noticing, the fault sits there silently until the day it combines with a second event into a failure. Built-in self-test exists so that the part can notice.
BIST is not a single block. Two kinds appear in almost every serious SoC. Logic BIST drives the scan chains with a pseudo-random pattern generator and compacts the responses into a signature; memory BIST walks algorithmic patterns across embedded SRAM and ROM through a wrapper around each memory. We cover the architecture of both on the built-in self-test service page; here the interesting question is why they are built the way they are.
The constraint that shapes everything is that there is no tester present. Logic BIST cannot rely on a stored library of patterns applied from outside, so it generates them on the fly with a linear-feedback shift register — pseudo-random, but deterministic and repeatable. And it cannot ship a reference waveform to compare against, so it compacts every response into one number, a signature, and checks that single value. Both choices exist to make the test self-contained enough to run with nothing but the chip’s own clock.
The clever, slightly unsettling part of logic BIST is the signature. Over a BIST run the chip produces an enormous stream of response bits. A multiple-input signature register — a shift register with feedback — folds that whole stream into a single word. A good device always lands on the same signature; a faulty one almost always lands somewhere else.
“Almost” is doing real work in that sentence. There is a tiny probability that a faulty response stream happens to compact to the same signature as a good one — aliasing. The register width and the number of patterns are chosen so that probability is negligible, which is one of the quiet design decisions that separates a BIST that means something from one that just looks reassuring.
Memory BIST is less about cleverness and more about access. A modern SoC can carry hundreds of embedded memories, and almost none of them connect to the package pins. There is simply no way for a tester to reach them directly. If those memories are going to be tested at all — at the factory or ever again — the test engine has to sit next to them on the die.
Once that engine is there, it enables something the tester never could: repair. Built-in redundancy analysis and self-repair detect a failing row or column and swap in a spare, recovering a memory that would otherwise scrap an entire — expensive — die. On memory-dominated parts, that recovery is the difference between a viable yield and an uneconomic one.
For a long time BIST was justified mainly on tester cost. That argument still holds, but it is no longer the one that matters most. Functional-safety standards — ISO 26262 in vehicles, and its siblings in industrial and medical systems — require a demonstrated level of diagnostic coverage of random hardware faults, including latent faults: the ones that develop and hide over a part’s service life.
You cannot demonstrate coverage of a fault that appears in year eight with a test that ran only in year zero. Power-on self-test, run at every key-on, and periodic self-test, run quietly while the system operates, are among the main mechanisms that raise the diagnostic-coverage number in the safety analysis. The scheduling of those tests becomes part of the safety concept itself. For higher integrity levels, in-field BIST stops being an optimisation and becomes a thing you have to have.
None of this is free. Logic BIST adds the pattern generator, the signature register, control logic and test points — usually a low single-digit percentage of area — and its pseudo-random coverage leaves a residue of hard-to-detect faults that still needs a compact set of tester-applied ATPG patterns to close. Memory BIST area scales with how many memories you carry. Running the tests draws power, which has to be managed so a BIST run does not exceed the thermal or supply budget.
The decision that actually determines whether all this pays off is made early: at DFT architecture, before layout. Retrofitting self-test into a design that did not plan for it is the expensive path, and the one we are most often called in to avoid.
No, but that is where it becomes non-negotiable. Memory BIST is near-universal because embedded memories cannot be reached from the pins, and logic BIST is common wherever tester time is expensive. What safety-critical parts add is the in-field requirement: the self-test has to run at power-on and periodically, not just at the factory.
Power-on self-test adds milliseconds to seconds at start-up, which is budgeted into the boot time. Periodic in-field tests are scheduled into idle windows or run on blocks a slice at a time so they do not disturb the running function. The scheduling is part of the safety design, not an afterthought.
Because a tester is only present at the factory, and some blocks — embedded memories especially — have no connection to the pins at all. ATPG gives the highest targeted coverage, so it stays in the flow, but it cannot run at key-on in a vehicle and cannot reach a deeply embedded SRAM. BIST and ATPG are complementary, not competing.
The MISR compacts a long stream of test responses into a single word using a feedback shift register. A correct device always produces the same signature; any deviation almost certainly changes it. There is a vanishingly small chance two different fault responses alias to the same signature, which is why the register width and pattern count are chosen to keep that probability negligible.
If self-test, diagnostic coverage and a safety target are on your critical path, the time to plan them is before layout. Tell us the specification, the constraint and the deadline.