SILICON DESIGN

Built-In Self-Test

A tester checks a chip once, at the factory, through its pins. Built-in self-test puts the pattern generator and the checker on the die, so the chip can test itself — on the tester, at every power-on, and periodically for the rest of its life. For a safety-critical part, the self-test that runs in the field is not a cost saving. It is the requirement.

LBISTMBISTPRPG · MISRMarch algorithmsBIRA / BISRPower-on · in-fieldISO 26262

What it is Where it earns its place BIST vs ATPG Questions

Built-in self-test: logic BIST and memory BIST, driven from on-chip test access

WHAT IT IS

Two engines, both living on the die.

BIST is not one thing. Two kinds matter in almost every SoC, and they are designed differently because they test different structures.

Logic BIST (LBIST) — a pseudo-random pattern generator, an LFSR, drives the scan chains through the combinational logic, and a MISR compacts millions of responses into a single signature compared against a known-good value. It gives broad coverage without storing patterns, and it is the mechanism that can re-run at power-on because nothing external is needed.
Memory BIST (MBIST) — an on-chip engine walks March algorithms across embedded SRAM and ROM through a wrapper around each memory. Embedded memories usually have no path to the device pins at all, so there is no tester-based alternative: if the memory is going to be tested, the test has to be on the die.
Repair, where yield demands it — MBIST pairs with built-in redundancy analysis and self-repair (BIRA / BISR) to swap in spare rows or columns, recovering memories that would otherwise scrap the whole die. On large memory-dominated parts this is the difference between a viable yield and an uneconomic one.
Still complemented by ATPG — pseudo-random patterns miss a small set of hard-to-detect faults. A compact set of tester-applied ATPG patterns closes that gap, so BIST and ATPG are planned together rather than treated as alternatives.

WHERE IT EARNS ITS PLACE

Four reasons it is on the die, not on the tester.

Tester time is expensive — ATE seconds cost real money at volume. Moving pattern generation on-chip shortens the tester program and the per-part cost, which is why memory-heavy and high-volume parts lean on BIST hardest.
Some blocks have no pins — a deeply embedded SRAM or a block behind a hierarchy of logic cannot be reached from the package. BIST is not the cheaper option there; it is the only option.
Power-on self-test — a part that must be trusted at every start — a brake controller, a medical device, an industrial safety ECU — runs its BIST at key-on and refuses to proceed if the signature is wrong. A tester cannot be present for that.
Latent faults over a service life — a fault that develops years after manufacture is invisible to a one-time factory test. Periodic in-field BIST is what detects it before it combines with a second fault into a dangerous failure, which is exactly what functional-safety standards require you to demonstrate.

HOW IT COMPARES

BIST and ATPG do different jobs.

On-chip self-test versus tester-applied patterns
Approach	What it targets	When it runs	Main strength	Main cost
Logic BIST	Random logic via scan chains	Wafer, power-on, in-field	Self-contained; re-runnable in the field	Area for PRPG/MISR; pseudo-random coverage gap
Memory BIST	Embedded SRAM / ROM	Wafer, power-on, in-field	Only way to reach pin-less memories; enables repair	Area scales with memory count and size
ATPG + tester	Hard-to-detect stuck-at / transition faults	Factory only	Highest targeted coverage	Tester time and pin access; cannot run in the field

The right split between BIST and ATPG is decided at DFT architecture, before layout — retrofitting self-test into a design that did not plan for it is the expensive path.

WHERE THIS APPLIES

Industries this serves.

Automotive & Mobility Semiconductor Aerospace & Defence Healthcare & Medical

COMMON QUESTIONS

What engineers ask about this.

What is the difference between BIST and ATPG?

ATPG generates test patterns that an external tester applies through the chip's pins; BIST puts the pattern generator and the result checker on the die, so the chip tests itself. ATPG gives high, targeted coverage but needs expensive tester time and pin access; BIST trades a little silicon area for shorter tester time, access to blocks you cannot reach from pins, and — the part ATPG cannot do — the ability to run the same test at power-on and in the field.

What are LBIST and MBIST?

LBIST is logic BIST: a pseudo-random pattern generator (PRPG, an LFSR) drives the scan chains and a MISR compacts the responses into a signature compared against a known-good value. MBIST is memory BIST: an on-chip engine walks March algorithms (C-, C+, and variants) across embedded SRAM and ROM through a wrapper, which is the only practical way to test memories that have no connection to the device pins.

Can BIST run in the field, not just at manufacturing?

Yes, and that is often the point. A logic or memory BIST can run as a power-on self-test every key-on, and periodically while the system runs, to catch latent faults that develop over the part's life. For a classic ATE-only flow the chip is tested once at the factory and never again; in a vehicle or an industrial controller, in-field self-test is what keeps a fault from going undetected for years.

How does BIST relate to ISO 26262 and functional safety?

Functional safety standards require a demonstrated diagnostic coverage of random hardware faults, including latent faults. BIST is one of the main mechanisms that delivers it: power-on and periodic self-test raise the diagnostic coverage figure in the FMEDA, and the self-test scheduling becomes part of the safety concept. For higher ASIL targets it is usually not optional.

What does BIST cost in area and coverage?

Logic BIST adds the PRPG, MISR and control logic and some test points, typically a low single-digit percentage of area; its pseudo-random coverage is good but usually complemented by a small set of ATPG patterns for the hard-to-detect faults. Memory BIST area scales with the number and size of memories. The right balance between BIST and tester-applied ATPG is a per-project decision we plan at DFT architecture, not after layout.

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Built-In Self-Test

Two engines, both living on the die.

Four reasons it is on the die, not on the tester.

BIST and ATPG do different jobs.

Industries this serves.

What engineers ask about this.

What is the difference between BIST and ATPG?

What are LBIST and MBIST?

Can BIST run in the field, not just at manufacturing?

How does BIST relate to ISO 26262 and functional safety?

What does BIST cost in area and coverage?

Related work.

DFT and silicon test

RTL to GDSII

Verification methodology

Functional safety

Low-power design

Silicon root of trust

Bring us the difficult part.