A complex chip has a state space no directed test suite can enumerate. When the regression passes, it proves that the cases someone thought to write behave correctly — and nothing about the cases nobody thought of. The bug that reaches silicon is almost always in that unexamined region, which is why a green run is a starting point rather than a finish line. Verification is measured not by whether tests pass but by coverage: how much of the intended behaviour has actually been exercised.
Closing that space is a discipline, not a single tool. It begins with a verification plan that states what must be exercised, so coverage has a target and 'done' has a meaning rather than being a number collected in the abstract. Constrained-random stimulus with self-checking then covers the bulk of the reachable space quickly, and functional and code coverage measure progress against the plan. The first ninety percent closes fast; the effort lives in the stubborn remainder — the corners the random generator almost never reaches, which need directed tests aimed straight at them.
Some properties cannot be closed by simulation at all. Arbitration fairness, absence of deadlock, certain safety properties hold over a space so large that no practical amount of stimulus proves them, and there formal verification proves the property mathematically instead. Recognising which properties need formal, rather than grinding simulation against them, is part of genuine closure. And the temptation at the end — to waive the awkward last holes — is exactly the trap, because the waived corner is where the escape hides. Real closure means the untested space has been reached and shown empty, by stimulus or by proof, not declared closed.