Timing closure is the milestone everyone celebrates and the one that proves least. A block can meet timing on the report and still fail signoff — on power, on IR-drop, on an antenna rule, on a corner nobody checked — and getting a real SoC through all of the signoffs, together, is the work.
A digital SoC arrives at implementation as a netlist that meets timing in synthesis, and the temptation is to treat physical design as a formality. It is not: timing has to hold after real placement, clock tree and parasitics, across every process, voltage and temperature corner, and at the same time power, IR-drop, electromigration, antenna and physical-verification rules all have to close.
The traps are the interactions. Fixing timing packs cells and raises congestion; relieving congestion moves cells and breaks timing; both change the power grid and the IR-drop. A block that passes each signoff on its own can still fail because the fix for one broke another.
The programme is therefore run as convergence across all the signoffs at once, with the schedule risk sitting in the last corners and the last violations rather than the first ninety percent.
Stated before any of them had an answer.
Meeting timing in synthesis says little. It has to hold after placement, CTS and extraction, across every corner, alongside every other signoff.
A timing fix raises congestion; a congestion fix breaks timing; both move the power grid. Closing them together, not in turn, is the problem.
Ninety percent of violations close quickly. The schedule lives in the last corners and the handful of paths that resist every standard fix.
DRC, LVS, antenna and electromigration do not negotiate. A clean-looking block fails tapeout on a rule check that was left to the end.
The report says timing is met. Signoff asks whether power, IR-drop, physical rules and timing are all met at once — which is a different, harder question.
The scope of the work, rather than a capability list.
Rarely the subsystem that sounds difficult.
The final corners and the paths that resist every standard fix are where the schedule actually goes, not the first ninety percent.
The two forces break each other; the work is a placement that satisfies both rather than one at the other's expense.
A grid that looks fine statically droops under real switching; catching that needs activity-driven analysis, not a static check.
A block that passes each signoff separately can still fail because the fix for one violated another; convergence is across all of them.
Timing closed with power, IR-drop and physical verification, together, across every corner.
A GDSII that passes DRC, LVS and antenna, released rather than patched at the last corner.
The last violations closed by method, not by loosening a constraint until the tool stopped complaining.
An implementation flow the customer can re-run on the next revision rather than rediscover.
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Because timing in synthesis is an estimate. It has to hold after real placement, clock tree and extracted parasitics, across every corner, and at the same time power, IR-drop, electromigration and physical-verification rules all have to close. A block that meets timing on the report can still fail any of those, which is why signoff, not timing closure, is the milestone that matters.
The last corners and the handful of paths that resist every standard fix. The first ninety percent of violations close quickly; the remainder, and the interactions between timing, congestion and the power grid, are where the time actually goes.
That timing, power, IR-drop, electromigration and physical verification all pass together, across every process, voltage and temperature corner, on the same database — not that each passed at some point on some version. Signoff is the simultaneous condition, which is what makes it hard.
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