A serialiser sends data at multi-gigabit rates, and inside the die that data is clean because the interconnect is short and controlled. The moment the signal reaches the pins it enters a channel the chip designer often does not own — a package, a board, a connector, sometimes a cable — and that channel attenuates the high-frequency content the fast edges depend on, reflects at every impedance discontinuity, and adds jitter. At these rates the received signal is barely open; the receiver has to reopen it before it can recover a bit at all.
Reopening it is the work of equalisation. The transmitter pre-distorts the signal, boosting the high frequencies the channel will attenuate, and the receiver applies its own equalisation to undo the remaining loss and reflection, restoring an eye wide enough to sample reliably. Tuning both to a specific channel — enough boost to open the eye, not so much that it amplifies noise — is an iterative, channel-specific task, which is why a link that closes over an ideal channel can still fail over the real board it actually meets.
Two things make it unforgiving. Jitter is contributed by the transmitter, the channel and the recovery loop together, so the link only closes if the whole budget is accounted as one — a link that looks fine stage by stage can fail as a whole. And when the channel is outside the silicon team's control, the margin has to be robust to a board and connector that vary, which raises the bar over a fixed channel. Signoff, therefore, is bit-error-rate margin proven over the real channel across conditions, not a datasheet eye measured on an ideal one.