The link that leaves the chip is where the trouble starts.
Inside the die the data is clean; the trouble begins at the pins. A multi-gigabit SerDes has to push bits across a lossy, reflective channel and recover them at the far end, and whether it works comes down to equalisation, jitter and a link margin proven over the real board.
DomainSilicon, high-speed interfaces
PlatformsFaststream Silicon
ScopeSerDes design to link margin
Binding constraintRecover the bit over a channel that fights it
DisclosureRepresentative programme; customer not named
CONTEXT
Where this started.
A serialiser-deserialiser sends data at multi-gigabit rates over a channel — package, board, connector, cable — that attenuates high frequencies, reflects at every discontinuity and adds jitter. At those rates the received signal is barely open; the receiver has to equalise the channel back out and recover a clean bit.
Whether that works is set by the transmit pre-emphasis, the receive equalisation, the clock-recovery loop and how much jitter the whole path introduces, all against a channel the silicon designer often does not control. A link that closes over an ideal channel can fail over the real one.
So the bring-up is a link-margin problem: equalisation tuned to the channel, jitter budgeted across the path, and margin proven over the real board with real loss rather than a datasheet eye.
CHALLENGES
4 problems, named.
Stated before any of them had an answer.
01
The channel closes the eye
Loss and reflections attenuate and distort the signal until the received eye is nearly shut; the receiver has to reopen it by equalisation.
02
Jitter is a shared budget
Transmit, channel and recovery all contribute jitter; the link only closes if the whole budget is accounted, not each part in isolation.
03
The channel is not the designer's
The board, connector and cable are often outside the silicon team's control, yet the link has to close over them, so margin has to be robust.
04
Clock recovery must lock and hold
The receiver recovers timing from the data; the loop has to lock across conditions and track drift without losing bits.
ARCHITECTURE
How it was built.
The datasheet eye is measured on an ideal channel. The engineering is closing the link over the board it actually meets, with jitter and loss working against it.
CONTRIBUTION
What Faststream did.
The scope of the work, rather than a capability list.
Transmit equalisation — pre-emphasis tuned to pre-distort the signal for the channel it will cross.
Receive equalisation — undoing the channel's loss and reflections to reopen the received eye.
Clock and data recovery — a recovery loop that locks across conditions and tracks drift without losing bits.
Jitter budgeting — accounting transmit, channel and recovery jitter as one budget rather than in isolation.
Channel-aware margin — proving the link over the real board, connector and cable, not an ideal channel.
Link signoff — bit-error-rate margin verified across conditions rather than a single datasheet eye.
WHAT WAS HARD
The parts that consumed the schedule.
Rarely the subsystem that sounds difficult.
01
Equalising a real channel
Tuning transmit and receive equalisation to reopen an almost-closed eye over a specific lossy channel is the central, iterative work.
02
Owning the whole jitter budget
Because jitter is contributed by every part of the path, closing the link means budgeting all of it together, which is easy to get wrong piecemeal.
03
Robustness to an unknown board
When the channel is outside the team's control, the margin has to be robust to variation, which raises the bar over a fixed channel.
04
Recovery that never slips
A clock-recovery loop that locks on the bench but slips at a corner loses bits in the field; making it hold across conditions is subtle.
OUTCOME
What resulted.
Eye reopened
A received signal equalised back to a margin that recovers bits reliably.
Link closed over the real board
Margin proven over the actual channel, not an ideal one.
Jitter within budget
The whole-path jitter accounted so the link meets its bit-error-rate target.
Recovery that holds
A clock-recovery loop that locks and tracks across conditions.
Confidentiality
Customer projects are presented at property, capability, outcome and integration level. Customer names, internal architecture, confidential deliverables and commercial terms are not disclosed. Where a detail would identify a customer it is omitted rather than approximated. More is available under a non-disclosure agreement, within the limits the customer has agreed.
Why is a high-speed link harder outside the chip than inside?
Because inside the die the interconnect is short and controlled, so the data stays clean. The moment the signal leaves the pins it crosses a package, board, connector and possibly a cable, all of which attenuate high frequencies, reflect at discontinuities and add jitter. At multi-gigabit rates the received eye is nearly closed, and the receiver has to equalise the channel back out to recover the bit — which is where the real engineering is.
02
What is equalisation doing?
It is compensating for what the channel did to the signal. The transmitter pre-distorts the data (pre-emphasis) to anticipate the channel's loss, and the receiver applies equalisation to undo the remaining attenuation and reflection, reopening the data eye enough to recover bits. Tuning both to a specific channel, so the eye is open with margin over the real board, is the core iterative work of a SerDes bring-up.
03
Why budget jitter across the whole path?
Because jitter accumulates from every stage — the transmitter, the channel and the clock-recovery loop — and the link only closes if the total stays within budget. Accounting for each contributor in isolation misses how they combine, and a link that looks fine part by part can fail as a whole. Treating jitter as one shared budget across the path is what makes the closure honest.