Radiation does two unrelated things to a chip — it builds up a cumulative dose, and it causes instant single-particle events — and hardening is a stack of defences, not a single part. Here is what fails, how, and where you stop each one most cheaply.
Radiation does two unrelated things to a chip, and confusing them leads to the wrong fix. The first is total ionizing dose (TID): charge trapped in the oxides accumulates over the whole mission, slowly shifting transistor thresholds, raising leakage and drifting timing until the part falls out of specification. It is gradual, cumulative and, to a first approximation, predictable from the dose the part will see.
The second is a single-event effect (SEE): one energetic particle strikes one node and deposits enough charge to cause an event right then. It is instantaneous, statistical, and independent of how long the part has been running. A brand-new device can suffer one in its first second.
They need different answers. TID is fought with the process and the layout and by derating; single-event effects are fought with redundancy, error correction and, for the destructive ones, with how the power and the substrate are built.
Single-event effects split into recoverable and destructive. The soft ones corrupt state without damaging the silicon. A single-event upset (SEU) flips a bit in a register or memory. A single-event transient (SET) is a voltage glitch on a combinational node that becomes an error if it is latched. A single-event functional interrupt (SEFI) puts a block into a bad state — a stuck state machine or a corrupted control register — that usually needs a reset.
The hard ones destroy the part. Single-event latch-up (SEL) triggers a parasitic thyristor that shorts power to ground; unless the current is cut in time the device burns out. Single-event gate rupture (SEGR) and burnout (SEB) punch through gate oxide or destroy a power transistor outright. These are not corrected after the fact — they have to be prevented, or the current limited fast enough to survive them.
Process (rad-hard by process, RHBP). Building on silicon-on-insulator or a dedicated hardened process removes the parasitic structure behind latch-up and reduces charge collection. It is the strongest defence and the most expensive, and the foundries that offer it are few.
Layout (rad-hard by design, RHBD). On an ordinary process, careful layout buys a great deal: enclosed-layout transistors that cut dose-induced leakage, guard rings that break the latch-up path, and spacing that stops one strike from upsetting two redundant nodes at once.
Architecture. Triple modular redundancy (TMR) votes three copies so one upset loses; error-correcting codes (ECC/EDAC) catch and fix memory bit-flips; and scrubbing continuously rewrites configuration memory — essential for an SRAM FPGA in orbit — before errors accumulate. System. A watchdog recovers a hung block, a current-limiting power design survives a latch-up, and derating keeps margins as TID erodes them.
The environment sets the requirement. Space sees heavy ions and protons and a TID budget that depends on orbit and shielding; avionics and even ground-level equipment see atmospheric neutrons that cause single-event upsets; nuclear and some medical and particle-physics settings have their own dose and flux. The higher the stakes and the harder the part is to reach, the more hardening earns its cost.
True rad-hard parts are expensive, slow to procure and often a generation or two behind commercial silicon. So a common modern approach is rad-hard by design on a commercial process plus system mitigation: start from a capable COTS device, characterise it under radiation, and wrap it in TMR, ECC, scrubbing and latch-up protection. It trades a known, managed upset rate for access to modern performance and a far lower bill.
Whichever route, the work is specific: know the environment and the dose, decide which effects are merely soft and which are mission-ending, and put a defence against each at the cheapest layer that will hold.
Designing an electronic part to keep working under ionizing radiation. It covers two problems: cumulative total-ionizing-dose degradation that builds up over a mission, and single-event effects caused by individual particles. Each is addressed with different techniques spanning the process, the layout, the architecture and the system.
Total ionizing dose (TID) is cumulative — trapped charge slowly shifts thresholds and raises leakage until the part drifts out of specification. A single-event effect (SEE) is instantaneous — one particle causes an event immediately, independent of how long the part has run. TID is fought with process and layout; SEE with redundancy and error correction.
A bit flip caused by one particle depositing charge in a storage node, corrupting a register or memory value without damaging the silicon. It is recoverable — caught by error-correcting codes, outvoted by triple modular redundancy, or cleared by scrubbing and reset.
A particle triggers a parasitic thyristor in the device that shorts power to ground. Unless the current is cut quickly the part overheats and is destroyed. It is prevented by a hardened or silicon-on-insulator process and guard-ring layout, and survived by current-limiting power design.
Running three copies of a circuit and voting their outputs, so a single-event upset in one copy is outvoted by the other two. It is a core architectural defence against soft errors, widely used in rad-hard FPGA and ASIC designs, at the cost of roughly three times the logic.
Often, with care. A common approach is rad-hard by design on a commercial process: characterise a capable COTS device under radiation, then wrap it in TMR, ECC, scrubbing and latch-up protection. It trades a managed upset rate for modern performance and far lower cost than full rad-hard silicon.
Catching faults in the field.
KNOWLEDGEWhere SOI and hardened fabs sit.
KNOWLEDGEWhat verification cannot see.
KNOWLEDGEThe other reliability problem.
KNOWLEDGEWhere mitigation is cheapest.
SOLUTIONWhere the parts have to survive.
Which effects are merely soft and which are mission-ending, and the cheapest layer to stop each, is the whole design. Tell us the orbit, the flux and the part.