Where is this role based?
Bengaluru, India. Full time, on our silicon team.
Silicon · Front-end RTL · Bengaluru
Principal ASIC Designer — Microcontrollers (MCU)
Own the front-end RTL of a microcontroller SoC — the micro-architecture, the finite state machines and datapath, the FIFOs and the clock-domain crossings, the AMBA bus fabric and the peripheral interfaces (UART, SPI, I²C, QSPI, USB) that connect the CPU, memory and the outside world. A front-end role: spec to a clean, verified netlist handed to the back-end team.
THE WORK
What the role involves.
- Define the micro-architecture of a microcontroller SoC — block partitioning, datapath, memory map and the register interface — and turn it into RTL.
- Write synthesisable Verilog and SystemVerilog: finite state machines, FIFOs, arbiters, counters and the control logic that actually runs the chip.
- Design the clocking and reset architecture and the clock-domain crossings — the synchronisers and FIFOs that make multi-domain logic safe.
- Integrate the CPU subsystem (Arm Cortex-M or RISC-V) and the AMBA (AHB/APB) bus fabric, with the memory, interrupt and DMA controllers around it.
- Design the peripheral blocks to their protocol specifications and corner cases — UART, SPI, I²C, QSPI/OSPI flash, USB, CAN-FD, timers/PWM and GPIO.
- Keep lint and CDC clean as a condition of check-in, and work alongside verification so coverage closes against the spec rather than after it.
- Lead a small front-end team and own the RTL deliverable the synthesis, DFT and physical-design teams build from.
TO APPLY
Send us something specific.
A CV is fine. What helps more is a paragraph about a block of RTL you are proud of — a tricky state machine, a clock-domain crossing you got right, a bus fabric or a FIFO under real backpressure — what made it hard and what you would do differently now. Apply through our application form — attach your résumé and write a cover letter. The cover letter is required.
COMMON QUESTIONS
What engineers ask before they call.
What experience is expected?
12+ years, at a principal level — someone who has owned the front-end RTL of microcontroller or SoC designs, not just contributed blocks. The number is a guide, not a filter.
Does this role include DFT or physical design?
No. This is a front-end role — micro-architecture, RTL, finite state machines, FIFOs, clock-domain crossings and integration. DFT, synthesis and physical design sit with the back-end team you hand clean, verified RTL to.
How do I apply?
Apply through the application form. A résumé and a cover letter are both required — the cover letter is not optional.
KEEP READING
Related work.
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