Where is this role based?
Bengaluru, India. Full time.
Silicon · Bengaluru, India
RTL Design and Verification Engineer
RTL design and constrained-random verification for digital and mixed-signal parts.
THE WORK
What the role involves.
- RTL implementation against a specification, with clock and reset architecture designed rather than inherited.
- UVM testbench development, coverage closure and formal property verification where it fits.
- DFT awareness, because test structures change timing and area.
TO APPLY
Send us something specific.
A CV is fine. What helps more is a paragraph about a problem you solved that was harder than it looked, and what you would do differently now. Write to careers@faststreamtech.com with the role title in the subject.
COMMON QUESTIONS
What engineers ask before they call.
What experience is expected?
3–8 years. The range is a guide rather than a filter — make the case if you are outside it.
How do I apply?
Write to careers@faststreamtech.com with the role title in the subject, and include a paragraph about a problem you solved that was harder than it looked.
KEEP READING
Related work.
BUILD WITH FASTSTREAM
Bring us the difficult part.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.