Digital fails with an error; analog just gets worse. On a mixed-signal SoC the danger is not a crash but a quiet loss of margin — coupling, substrate noise, supply sag — that no functional test catches and that only shows up as yield or field drift once the part is built.
A mixed-signal SoC puts sensitive analog and RF next to noisy, switching digital on one die. The digital works or it does not; the analog degrades — a converter loses bits, a PLL gains jitter, a reference drifts — and none of it announces itself in a functional test.
The mechanisms are physical and shared: substrate noise from the digital couples into analog wells, supply and ground bounce ride the shared grid, and a floorplan that puts an aggressor next to a victim guarantees the problem before a transistor is placed.
So the integration is governed by isolation and floorplan discipline from architecture onward, and validated by post-layout signoff that models the coupling rather than assuming it away.
Stated before any of them had an answer.
Analog degradation does not crash; it drifts. A converter that loses effective bits or a PLL that gains jitter passes every functional test and fails in yield or the field.
Substrate, supply and ground are shared between the noisy digital and the sensitive analog, so the digital's switching reaches the analog unless the design actively stops it.
Put an aggressor next to a victim and no later fix recovers it. Isolation is a floorplan decision made before placement, not a patch after it.
Schematic-level analog looks clean; the parasitics and coupling that degrade it appear only after layout, so signoff has to model them.
The analog and the digital share a die but must not share noise. Isolation is designed in from the floorplan and proven in post-layout signoff.
The scope of the work, rather than a capability list.
Rarely the subsystem that sounds difficult.
You cannot functionally test for lost margin; you have to model the coupling and show it stays within budget, which is harder than catching a crash.
Because isolation is decided before placement, getting the partition and floorplan wrong is expensive to undo, so most of the thinking is front-loaded.
Coupling and parasitics that were invisible in schematic appear after layout, so the signoff loop has to be planned for, not discovered.
A reference or a converter that is fine at typical drifts at a corner; the margin has to hold across all of them, which multiplies the analysis.
Converter effective bits, PLL jitter and reference drift kept within budget across corners, not just at typical.
Substrate, supply and ground isolation proven in post-layout, so the digital's switching does not reach the analog.
Analog signoff on extracted, coupled layout rather than optimistic schematic.
A part whose analog behaves in production because the degradation mechanisms were designed out, not discovered.
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Every item links to its own page.
Coupling and floorplan.
SERVICEConverters, PLLs, PMICs.
PLATFORMThe silicon platform.
SERVICEArchitecture to physical.
PRODUCTData-converter cores.
TECHNOLOGYWhere coupling bites hardest.
Because the blocks share a die, a substrate and a supply. The digital switches and that noise couples into the analog, which does not fail cleanly — it loses margin. A converter drops effective bits, a PLL gains jitter, and none of it shows in a functional test, so the integration, not the individual blocks, is where the risk is.
Because isolation is a floorplan decision. Put a switching aggressor next to a sensitive victim and no later routing or tuning recovers the lost margin. The partition and floorplan are settled before placement, which is why most of the engineering is front-loaded.
Because analog degradation is not a functional error. The part still works; it just works worse — less signal-to-noise, more jitter, more drift. That only surfaces as yield loss or field drift, so it has to be caught by modelling the coupling in post-layout signoff, not by a pass/fail test.
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