SILICON DESIGN

Physical Design & Timing Closure

Getting a netlist to behave on silicon is where the easy problems end. Floorplan, placement, clock tree and routing all interact, and a change that fixes timing in one corner can open congestion, IR drop or an electromigration violation somewhere else. Closure is the craft of making all of those true at once — and knowing, when a block will not close, whether the answer is a tool setting or the architecture.

FloorplanPlacementCTSRoutingCongestionMCMM timingIR · EMSignoff

The closure loop What is hard Questions

Where congestion shows up, and the place–route–analyze loop that closes a block

WHAT IS ACTUALLY HARD

The problems that decide the schedule.

None of these is the individual step. They are the interactions — and the judgement about when a block has stopped being a tool problem.

Congestion and routability — routing demand exceeding the tracks available, clustered around macros and dense logic. It is set at placement and floorplan, not fixed by routing harder. Above ~80% utilisation the router has no freedom and closure becomes architectural.
Timing closure across MCMM — meeting setup and hold across every process, voltage and temperature corner and every functional mode together. A fix that helps one corner can break another, which is why corners are closed jointly rather than in sequence.
IR drop and power integrity — the supply sags under switching current, so cells slow down exactly when they switch. Timing closed at nominal voltage fails in silicon unless the power grid and placement are signed off against real current.
Electromigration — wires can only carry so much current over a ten-year life. A late EM violation can force a grid or placement change that reopens timing already thought closed.
Crosstalk and signal integrity — aggressor nets coupling into victims change delay and can cause functional noise failures. Closed with spacing, shielding and net ordering, all of which cost area and routing resource.
Thermal — local hotspots shift timing and reliability. On dense, high-power blocks the floorplan has to account for where the heat goes, not only where the logic fits.

HOW WE WORK

Closure planned, not discovered.

A provisional floorplan, revised on purpose — an early floorplan explicitly marked provisional, with one revision budgeted after first routing shows the real congestion. The alternative — freezing it early — is the most common and expensive mistake.
Constraints reviewed as their own activity — a design that closes against constraints which over-relax a path passes signoff and fails in silicon. Constraint review has its own reviewer, separate from synthesis.
Congestion read early — a first trial route to see where the overflow is before placement is committed, so the floorplan and utilisation can respond while there is still time to iterate.
Signoff against real conditions — MCMM timing, IR, EM, crosstalk and thermal closed together, because the interactions between them are where late surprises live.

WHERE THIS APPLIES

Industries this serves.

Semiconductor Consumer Electronics Automotive & Mobility Aerospace & Defence

COMMON QUESTIONS

What engineers ask about this.

Why does a design fail to close timing?

Usually not for one reason. The common ones are a floorplan that fixed macro positions before the real congestion was known, constraints that do not describe the true intent, clock trees that spend their skew budget badly, and utilisation pushed so high the router has no freedom. Above roughly 80% utilisation, closure stops being a tool-settings problem and becomes an architectural one — the honest fix is to change the floorplan or the micro-architecture, not to keep tuning.

What causes routing congestion, and how is it fixed?

Congestion is local demand for routing tracks exceeding supply — it clusters around hard macros, high pin-density cells and over-tight placement. You see it on a congestion map as overflow hotspots. The fixes are placement-level (spread the cells, add blockages and halos around macros, cut the local utilisation) and floorplan-level (move the macros that are causing it). Routing harder rarely helps; it is decided upstream.

What is multi-corner multi-mode (MCMM) closure?

A modern part must meet timing across many process, voltage and temperature corners and in several functional modes at once — functional, test, low-power. MCMM closure optimises against all of them together rather than one at a time, because a fix at one corner can break another. It is the difference between a block that closes on paper and one that works across every silicon you will actually receive.

How do IR drop and electromigration affect closure?

They move it from a timing problem to a physical one. IR drop means the supply sags under switching current, so cells run slower exactly when they switch — timing signed off at nominal voltage then fails. Electromigration limits how much current a wire can carry over the part’s life. Both are signed off alongside timing, and a late IR or EM violation can force a power-grid or placement change that reopens timing.

When should physical design start?

Earlier than most plans assume. An early, explicitly provisional floorplan — with one revision budgeted after first routing — beats a floorplan frozen before congestion is known. Test insertion, power intent and the bring-up plan all change the physical result, so they belong in the plan from the start rather than bolted on after synthesis.

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Related work.

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Physical Design & Timing Closure

The problems that decide the schedule.

Closure planned, not discovered.

Industries this serves.

What engineers ask about this.

Why does a design fail to close timing?

What causes routing congestion, and how is it fixed?

What is multi-corner multi-mode (MCMM) closure?

How do IR drop and electromigration affect closure?

When should physical design start?

Related work.

RTL to GDSII

Routing congestion & P&R failures

Low-power design

Post-silicon validation

Agentic chip design

DFT and silicon test

Bring us the difficult part.