Where is this role based?
Bengaluru, India, or the United States — this role is open in both. Full time.
Silicon · India & US
Digital ASIC / SoC Architect
Own the micro-architecture of a chip — block partitioning, datapath, interconnect and the power, performance and area trade-offs made before a line of RTL is written.
THE WORK
What the role involves.
- Define the chip and SoC architecture — block partitioning, datapath, interconnect and memory hierarchy — before RTL begins.
- Own the power, performance and area budgets, and the architectural trade-offs behind them.
- Choose IP, interfaces and the micro-architecture the RTL and verification teams implement.
- Set the architecture sign-off criteria, and stand in front of customers on design-services programmes.
TO APPLY
Send us something specific.
A CV is fine. What helps more is a paragraph about a problem you solved that was harder than it looked, and what you would do differently now. Apply through our application form — attach your résumé and write a cover letter. The cover letter is required.
COMMON QUESTIONS
What engineers ask before they call.
What experience is expected?
8–18 years. The range is a guide rather than a filter — make the case if you are outside it.
How do I apply?
Apply through the application form. A résumé and a cover letter are both required — the cover letter is not optional.
KEEP READING
Related work.
BUILD WITH FASTSTREAM
Bring us the difficult part.
Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest.