Writing correct power intent is the easy part; keeping it true through implementation is not. A multi-domain SoC lives or dies on isolation, level shifting, retention and gating that must survive synthesis, place-and-route and signoff intact — because intent that is right at RTL and lost downstream fails silently in silicon.
A low-power SoC switches parts of itself off — power domains that gate, retain state, and hand signals across voltage boundaries. That intent is captured in UPF: which domains exist, how they isolate, where level shifters go, what retains across a shutdown. Written correctly, it describes a chip that saves power without corrupting itself.
The danger is downstream. Synthesis, place-and-route and optimisation each transform the netlist, and an isolation cell dropped, a level shifter missed at a domain crossing or a retention strategy that did not survive can leave intent that reads correctly at RTL but is violated in the implemented chip — and none of it shows up in a functional test at typical conditions.
So the programme treats power intent as something to be preserved and verified at every step: consistent UPF across the flow, power-aware implementation, and signoff that checks isolation, level shifting and retention on the real netlist, not just the specification.
Stated before any of them had an answer.
An isolation cell or level shifter dropped in optimisation produces a netlist that passes functional simulation and fails at a domain crossing in silicon.
Every signal between two domains at different voltages or power states needs isolation or level shifting; miss one and the chip corrupts when a domain gates.
State that must survive a power-down needs retention cells wired and verified; a retention strategy that did not carry through loses the state it promised.
Power intent verified against the specification proves nothing if the implemented netlist diverged; the checks have to run on the real thing.
UPF describes the chip you meant to build. Signoff proves the chip you actually built still isolates, shifts and retains — because implementation can quietly lose all three.
The scope of the work, rather than a capability list.
Rarely the subsystem that sounds difficult.
An isolation cell dropped in optimisation leaves no functional symptom at typical conditions; catching it needs power-aware verification on the real netlist, not a functional test.
There are many domain boundaries and every one needs handling; the discipline is exhaustive rather than clever, and one miss is a failure.
Keeping a retention strategy intact across the whole flow is harder than specifying it; the verification has to prove the state survives, not assume it.
The value is in checking the implemented netlist against the intent; a check against the spec alone misses exactly the divergence that matters.
Isolation, level shifting and retention intact in the implemented netlist, not just the UPF.
Domain crossings verified power-aware, so a dropped cell is caught in signoff rather than in silicon.
Retention proven across power-down, so the chip wakes with the state it promised.
A power-aware implementation flow the customer can re-run without re-losing the intent.
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Because the intent written in UPF at RTL passes through synthesis, place-and-route and optimisation, each of which transforms the netlist. If an isolation cell is dropped, a level shifter is missed at a voltage crossing, or a retention strategy does not carry through, the implemented chip violates the intent while still passing functional simulation at typical conditions. The failure is silent until a domain actually gates in silicon.
They are the mechanisms that make multiple power domains safe. Isolation clamps signals leaving a domain that is powered down so they do not corrupt a domain that is awake; level shifters translate signals between domains at different voltages; and retention cells preserve chosen state through a power-down so the domain can resume. Every domain crossing needs the right one, and all three must survive implementation.
Because the specification is what you intended and the netlist is what you built, and the whole risk is that they diverged. Power-intent verification run against the UPF specification confirms the intent was written correctly but says nothing about whether implementation preserved it. Running the isolation, level-shift and retention checks on the actual implemented netlist is what catches the silent loss.
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