A chip that passes every simulation can still ship defects the tester never checks. Design-for-test is what makes manufacturing faults reachable from the pins — and doing it without exploding test time or area is a discipline that has to be designed in, not bolted on after the netlist freezes.
Functional simulation proves a design does what it should. It says almost nothing about whether a manufactured die is free of defects — a bridged net, an open via, a stuck node. Catching those is the job of manufacturing test, and manufacturing test can only catch a fault it can reach and observe.
Design-for-test makes the internal state reachable: scan chains stitch flip-flops into shift registers, compression squeezes the test data so the pattern set fits the tester, and ATPG generates the patterns that toggle and observe each fault. Skip it and coverage is a guess; do it badly and test time and pin count blow the cost budget.
So DFT is planned as part of the design, not after it: scan architecture chosen against the test budget, compression ratio traded against coverage, and a pattern set signed off on real fault models rather than an optimistic percentage.
Stated before any of them had an answer.
A design can be functionally perfect and still yield dies with bridges and opens; only structural test catches those, and only if the faults are reachable.
A fault ATPG cannot toggle and observe is uncovered, however good the number looks; unreachable logic has to be found and fixed in the DFT, not papered over.
Every pattern costs tester seconds across every die; compression and pattern efficiency decide whether the test is affordable at volume.
Scan insertion touches timing and area; done late it fights physical design, so it has to be planned in from the start.
Coverage is only real if ATPG can reach the fault. DFT designs that reachability in — and keeps the pattern set inside a test budget that survives volume.
The scope of the work, rather than a capability list.
Rarely the subsystem that sounds difficult.
The first ninety percent of faults are easy; the remaining reachability gaps — deep state, redundant logic — are where the DFT effort actually goes.
Higher compression cuts test time but can cost coverage; finding the ratio that keeps both acceptable is the trade at the centre of the work.
Catching timing-related defects means testing at speed, which stresses the scan clocking and the pattern generation far more than stuck-at.
Scan and test logic add area and timing paths; planned late they collide with place-and-route, so the DFT has to lead, not follow.
Fault coverage signed on models ATPG can actually reach, not an optimistic number with hidden gaps.
A compressed pattern set whose tester time survives production volume.
Timing-related faults covered, not just static stuck-at.
A test architecture the customer can carry to the next device rather than reinvent.
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Because simulation and manufacturing test answer different questions. Simulation proves the design is functionally correct; the tester checks whether a specific manufactured die is free of physical defects like bridges, opens and stuck nodes. Those defects have nothing to do with the design's correctness, and the tester can only catch one if design-for-test has made that fault reachable and observable from the pins.
It is the fraction of modelled manufacturing faults that the test patterns can both activate and observe. The trap is that a high headline number can hide faults ATPG simply cannot reach because the logic is uncontrollable or unobservable — those are uncovered no matter what the percentage says. Real coverage closure means finding those reachability gaps and fixing them with test points, not reporting around them.
Because scan chains, compression logic and test points change timing, area and clocking. If DFT is added after the netlist and floorplan are settled, it collides with physical design and forces rework. Planned from the start, the test architecture and the physical design converge together, and the test budget is met without a late, expensive scramble.
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