WIRELESS & RF · FPGA

RF Signal Processing on FPGA

Q: Can the FPGA design migrate to an ASIC later?

Yes the RTL is written so it can move to an ASIC when volume justifies the NRE, which is a path we handle end to end through our FPGA-to-ASIC conversion service.

The digital front end of a modern radio is an FPGA problem. DUC and DDC, CFR and DPD, FFTs, filters and channelizers all run in fabric at line rate — and on an RFSoC the RF data converters sit on the same device, sampling RF directly. We design that DSP and close it in real FPGA timing.

RFSoCDUC/DDCCFR · DPDFFT · filtersChannelizersTiming closure

On the device What we build Why FPGA Questions

RF straight into FPGA fabric — the whole digital front end on one device

WHAT WE BUILD

The DSP that becomes the radio.

Digital up/down conversion — interpolation, decimation and NCO mixing to move between baseband and the converter sample rate.
CFR and DPD — crest-factor reduction and digital predistortion in fabric, closing the loop with the PA to hold ACLR and EVM.
FFT, filters and channelizers — OFDM transforms, FIR/CIC filtering and polyphase channelizers, sized for real throughput.
RFSoC integration — direct-RF sampling converters and the fabric DSP on one device, with the clocking and real-time timing closure that makes it work.

WHY FPGA

Deterministic, at line rate.

Real-time determinism — wireless PHY lives inside hard sample-rate deadlines that a CPU cannot guarantee; fabric does.
Parallelism — wide, pipelined datapaths process every sample every cycle, which is how multi-gigasample radios are built.
Timing closure is the work — at hundreds of MHz across a full DFE, closing timing and managing DSP/BRAM resources is the real engineering.
Path to ASIC — the same RTL can migrate to an ASIC when volume justifies it, which we also do.

COMMON QUESTIONS

What engineers ask about this.

Do you design on RFSoC devices?

Yes. RFSoC-class devices put wideband RF ADCs and DACs on the same die as the programmable logic, so the whole digital front end — DDC/DUC, CFR, DPD, FFT, filtering — runs in fabric with direct-RF sampling and no separate transceiver board. We design that DSP and close its timing.

Which DSP blocks do you implement in FPGA?

Digital up- and down-conversion, crest-factor reduction, digital predistortion, FFT/iFFT, FIR and CIC filters, and polyphase channelizers — the full 5G digital front end. These are available as IP and as custom designs sized to the throughput and resource budget.

Can the FPGA design migrate to an ASIC later?

Yes — the RTL is written so it can move to an ASIC when volume justifies the NRE, which is a path we handle end to end through our FPGA-to-ASIC conversion service.

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Related work.

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RF Signal Processing on FPGA

The DSP that becomes the radio.

Deterministic, at line rate.

What engineers ask about this.

Do you design on RFSoC devices?

Which DSP blocks do you implement in FPGA?

Can the FPGA design migrate to an ASIC later?

Related work.

5G digital front end

DPD IP core

Polyphase channelizer IP

FPGA design

FPGA-to-ASIC

RF front end & transceivers

Bring us the difficult part.