Architecting the silicon and the software together, so the chip is built for the workload it has to run — not enabled for it afterwards. We partition the workload across hardware and software, stand up models so software starts before RTL is finished, and keep one workload runnable from virtual prototype through to silicon.
In the AI era the workload defines the product and the hardware is its execution platform. That inverts the usual order — the software can no longer be enabled after the silicon is fixed. Faststream engages semiconductor work as a co-design programme: the workload shapes the architecture, and the architecture is validated against real software long before tapeout.
We start from the workload and a specification precise enough to build both sides against. We partition, then bring up an executable model so software can begin. As RTL matures we move the same workload up the abstraction ladder — virtual prototype, emulation, FPGA prototype — so each result carries to the next, and the software is already running when silicon arrives. The architecture-level trade-offs stay with experienced architects; the mechanical work is accelerated with the right tooling.
Co-design sits ahead of implementation and draws on the rest of the silicon-design stack.
Architecture through tapeout.
SERVICEThe implementation flow.
SERVICEUVM, coverage, formal.
SERVICEDrivers, BSPs, bring-up.
CAPABILITYWorkload-shaped datapaths.
INSIGHTThe reasoning, in full.
Architecting the silicon and the software that runs on it together — partitioning the workload across hardware and software, standing up virtual prototypes so software starts before RTL is done, and co-verifying across abstractions so the two meet at tapeout rather than after it.
It sits in front of it. Co-design decides what should be hardware and what should be software, and shapes the architecture the ASIC/SoC programme then implements through RTL, verification, DFT and physical design.
Yes — against a virtual prototype (typically SystemC) and, later, emulation and FPGA prototypes. The same representative workload is kept runnable across all of them so results carry from one level to the next.
A partitioning and architecture decision with the trade-offs made explicit, virtual/executable models, an early software bring-up path, a co-verification environment across abstractions, and performance and power analysis that informs the architecture rather than confirming it late.
AI and workload-defined silicon, where the architecture must be shaped by the software it runs; and any programme where getting software running early materially de-risks the schedule.
Tell us the workload and the constraints. Partitioning hardware and software together, and proving it before tapeout, is how Faststream runs semiconductor programmes.