What is a DROIC?
A Digital Read-Out Integrated Circuit — the read-out chip bonded to an imaging array. Here it integrated the analog signal chain with only minimal digital logic, exposing LVDS image data and a serial programming interface.
SENSOR VALIDATION
Validating a 2,000-frame-per-second image sensor with an FPGA.
A high-frame-rate image sensor cannot be evaluated by pointing a host at it. At around two thousand frames a second the data arrives faster than software can reliably accept, and the people who need the images — the analog designers of the read-out circuit — need them captured deterministically, not best-effort.
CONTEXT
Where this started.
The DROIC under test integrated the analog signal path with only minimal digital logic: an LVDS interface for image data and a serial programming interface. Everything else — acquisition timing, framing, and getting the images off the board fast enough to be useful — had to live in an FPGA sitting between the sensor and the host.
The sensor targets industrial and military use and images in both the infrared and visible bands, so the acquisition had to be exact rather than approximate: the characterisation is only as trustworthy as the capture beneath it.
CHALLENGES
4 problems, named.
Stated before they had answers.
01
The sensor outruns the host
At ~2,000 fps the image stream exceeds what a host can capture directly, so acquisition and buffering had to move into the FPGA.
02
The DROIC is almost all analog
With only minimal digital logic on the sensor, the FPGA had to provide LVDS capture, framing and the serial programming interface itself.
03
Getting frames off the board
A single link could not carry the rate, so the images had to be split across two high-speed paths to the host without loss or reordering.
04
Capture has to be exact to be useful
Characterisation feeds the analog design team, so any artefact introduced in acquisition would be mistaken for a sensor property.
ARCHITECTURE
How the system was built.
The FPGA sits between an almost-all-analog sensor and a host that cannot keep up. A framing state machine captures the LVDS image stream into DDR4, and two FX3 SuperSpeed controllers carry it to the host at roughly 5.2 Gbps combined, where the images are processed offline to characterise the DROIC and feed the sensor manufacturer's analog teams.
CONTRIBUTION
What Faststream did.
The specific scope, rather than a capability list.
- FPGA design on Kintex UltraScale — interfacing and characterising a ~2,000 fps DROIC image sensor.
- LVDS acquisition — capturing the sensor's image stream and driving its serial programming interface.
- Acquisition state machine — deterministic frame timing and control on the FPGA fabric.
- Dual USB 3.0 datapath — two FX3 SuperSpeed controllers streaming acquired images to the host at ≈5.2 Gbps.
- Frame buffering — DDR4-backed buffering sized to the sensor's frame rate.
- Host-side tooling — offline processing to characterise the DROIC and feed the analog design team.
WHAT WAS HARD
The parts that consumed the schedule.
Written out because a reader facing the same programme gets more from this than from a summary of what went well.
01
The sensor outruns the host
Acquisition and buffering were moved into the FPGA so frames are captured deterministically rather than best-effort.
02
Splitting the stream without loss
Dividing the image stream across two USB 3.0 controllers meant getting ordering and flow control right so the host reassembles frames intact.
03
Exact capture for trustworthy characterisation
Because the images feed analog design decisions, the datapath was designed to add nothing of its own to the sensor's output.
04
IR and visible in one path
Supporting both bands meant the acquisition could not assume a single data format or range.
OUTCOME
What resulted.
A deterministic ~2,000 fps capture path
LVDS acquisition, framing and buffering on the FPGA, capturing the sensor at full rate.
Images on the host at ≈5.2 Gbps
Dual USB 3.0 SuperSpeed links delivering acquired frames fast enough to be characterised in bulk.
Characterisation feedback to the sensor maker
Offline processing that turned captured images into feedback for the analog design teams.
A reusable sensor bring-up rig
An FPGA-based interface and acquisition pattern reusable for other high-rate sensors.
Confidentiality
Customer projects are presented at property, capability, outcome and integration level. Customer names, internal architecture and confidential deliverables are not disclosed. Where a figure would identify a customer or a design, it is omitted rather than approximated. More detail is available under a non-disclosure agreement, within the limits each customer has agreed.
CAPABILITY USED
What this was built from.
Every item links to its own page.
PLATFORM
Faststream Silicon
FPGA and SoC design.
SERVICEFPGA Design
Architecture, HDL, timing closure.
CAPABILITYHardware & High-Speed PCB
LVDS, SI/PI and bring-up.
SOLUTIONImage Processing & FPGA Vision
The wider body of imaging work.
CASE STUDYFPGA data-acquisition board
Another high-rate capture programme.
PRODUCTFPGA data-acquisition boards
High-speed capture hardware.
WHERE THIS APPLIES
Industries this serves.
COMMON QUESTIONS
Questions this programme gets asked.
Why use an FPGA to characterise a sensor?
Because the sensor runs faster than a host can capture directly, and the analog team needs deterministic high-rate acquisition an FPGA provides through LVDS capture, a framing state machine and a high-throughput link.
How is 5.2 Gbps to a host achieved?
Two USB 3.0 SuperSpeed (FX3) controllers run in parallel, each carrying part of the image stream, so frames reach the host at roughly 5.2 Gbps combined.
What does characterisation feed back to?
Images are processed offline on the host to characterise the DROIC and feed the sensor manufacturer's analog design teams — closing the loop between silicon and system.
KEEP READING
Related work.
BUILD WITH FASTSTREAM
Bring us the difficult part.
Tell us the sensor, the frame rate and the interface. High-rate acquisition and characterisation on FPGA fabric is core Faststream work.