In contrast to popular belief, the cost of a custom analog and mixed-signal ASICS silicon design has been thrifty in the last few years. This now permits more firms to think about developing their own device, customized to their project needs, and typically enveloping their intellectual property in a more secure, high-performance device.
Digital ASIC development at the leading side of process technology is an expensive business, with masks costing you millions of dollars. This has led many individuals to believe that they can not pay to design their own device, but for analog and mixed-signal Asics designs, the 0.35 micron and 0.18-micron process nodes are now totally mature well as could be really inexpensive.
These are still cutting edge designs yet the added value is in the design abilities of the engineer, as opposed to squeezing the last picosecond of clock rate from the device. Customized designs are significantly prominent for changing obsolete parts, as well as this sort of project could extend product lifetime at an affordable cost, particularly as the new version could be made pin-for-pin suitable with the old device.
There are issues with analog and mixed-signal Asics designs that simply having all the aspects under one roof prevents the problems that could make projects prohibitively costly and high risk.
While there are readily available analog and mixed-signal Asics design devices, progressively there are various aspects of the design to think about what could be costly if utilizing a pure-play foundry, stand-alone design as well as external test houses.
While a foundry could have numerous process technologies to offer, it might not provide the best combination of technology – from CMOS to BiCMOS or SiGe – at the ideal geometries. This could lead to the design trade off’s at the beginning. There are the various IP blocks that will be made use of, typically for the interfaces and analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
Designing your own ADC, DAC, or serial interface is possible, however, time-consuming to verify and test, and there are a lot of IP blocks available on the market– the foundry will have a collection optimized for its processes.
Discovering the right blocks, negotiating the rights, seeing to it that the IP is suitable for the process technology all requires time that detracts from the focus on the core of the project and could require compromises that will restrict the efficiency that the project requires.
Needing to utilize various processes even if an interface block is not available in the selected, optimal process does not make sense, so having IP blocks available, optimized for different process technologies, is a crucial requirement.
Usually, there is a mismatch between the functional verification of a design, maybe operating on FPGA with specific peripherals, and the translation to a custom device with a different, though functionally equal, collection of interfaces.
Having the ability to square that circle and make certain that the design does what the engineer meant, takes experience and knowledge. This likewise connects into the test and assurance which are connected to the design and to the process technology.
Making use of a foundry, maybe with the design working on an inexpensive Multi-Project Wafer (MPW) with other customers, could appear to be a cost-effective approach. These tools require to be packaged and evaluated, and that’s where the costs can unexpectedly rocket.
Testing the analog and mixed-signal Asics components of a chip is not a minor task and much of the test houses related to the foundries might not be up to the job, and as a designer, you have little control over the test coverage and the last yield. Instantly the cost and time considered for testing become to be a significant migraine as does quality assurance.
Having wafer probing and ATE testing that is closely paired with the test vectors made use of for the verification of the design on a specific process with the best design rules is challenging to accomplish unless it is all under one roof, and bringing all this with each other takes the substantial amount of management and experience.
Once the ASIC has been tested, it requires packaging. While the significant packaging houses have subsidiaries here in Europe, they might not have the specialist materials or qualification process that several analogs and mixed-signal ASICs design need, particularly for changing obsolete parts in military or industrial equipment.
Having the wafer test and final test available at a single site likewise substantially streamlines the traceability of the product, an additional crucial requirement in numerous quality systems.
Bringing all the components of an analog and mixed-signal Asics design under one roof enables the cost of each step of the process to be contained effectively. Handling each step of the design, manufacturing, and test of the device with different partners is time-consuming as well as could bring about big unanticipated costs when problems arise on the other side of the world.
Integrating these components with versatility in the selection of process technology as well as experience in chip design implies design and manufacturing issues could be swiftly and cost-effectively resolved.