FPGA to ASIC Conversion

FPGA TO ASIC CONVERSION

Faststream Technologies provides significant cost savings, performance enhancement, and product assurance in FPGA to ASIC conversation. Our customers have been able to reduce system costs considerably by successfully substituting their high-cost FPGAs with drop-in ASIC replacements in various applications. In most cases, higher performance, lower power, better thermal performance, and improved radiation immunity can be achieved in the ASIC. We supply a parallel development path for FPGA development. This leverages the inherent flexibility for developing a new generation wireless connectivity of an FPGA during the development phase while accelerating the path to low-cost production with an ASIC.

Faststream’s design Engagement

Faststream Technologies has worked on more than 500 IP and IP subsystems to support IP replacement or customization within the FPGA-to-ASIC conversion process.
Worked on Micro-Program Sequencing Engine for executing quick circuit function
We have completed ASIC/SoC design flow and methodology
We have worked on an SoC evaluation platform for software and hardware co-development and system evaluation in the early stage

Faststream offers the following types of conversion

FPGA Replacements

When 1 FPGA needs to be converted into 1 ASIC with pin-to-pin compatibility

Key Features

Faststream Technologies performs a turnkey design from the FPGA RTL code.
Pin-to-pin compatibility.
Faststream provides QML parts using its Rad Hard 0.5um or 0.35um ASIC libraries and technology.
Short cycle time (4-6 weeks from order entry to prototype delivery).
Low NRE or no NRE depending on flight production quantity.
No additional cost such as burn-in boards, qualification parts…

FPGA migration

When there is no pin-to-pin compatibility
When 2 or more FPGAs need to be converted into a single ASIC (multi-conversion).
When additional features are requested on the original FPGA design.
This solution is closer to the development of an ASIC which is based on the design as validated by the customer with the FPGA.

Faststream Technologies undergoes the following stages of FPGA migration

The customer performs the Front-End design using the appropriate libraries in 0.5um, 0.35um, or 0.18um ASIC families.
The customer delivers an ASIC net-list, formalized by a Logic Review.
Faststream performs the Back-End Design, formalized by a Design Review.
The package is selected from Faststream’s preferred package list (all space qualified).
Faststream provides QML parts using the selected libraries and technologies.

Our Customer Design Toolkit:

Gate and cell-based standard cell, compiled memory, IO, and analog IP for synthesis and simulation.
Logic rules checkers.
Tester rules checkers.
All design kits available via website download.
Design-for-test guidelines and requirements.
Design kit manuals.

Features of Our FPGA to ASIC conversation

Cost reduction for existing FPGA production volumes
Automatic design migration to an ASIC
Providing a pin for pin FPGA migration to ASIC
Integration of multiple FPGAs into one ASIC
Extending production support for End of Life FPGAs
Optional Conversion
RTL handoff
FPGA Netlist handoff

FPGA to ASIC Conversion: Benefits

Pin for pin device conversion-no board re-layout for technically feasible
Increased performance or performance margin
Significant reduction in power consumption
Overall Reduction in device BOM cost
Integration of multiple FPGAs into one
Smaller Structured ASIC devices and packages
Elimination of PROM/EPROM programming part

FPGA to ASIC Conversion Capabilities

Microsemi : RH1020, RH1280, RT54SX or RTAXS/SL FPGA designs Xilinx: XC2, XC3, XC4000S, XC8100, Virtex II, Virtex 4, Virtex 5, Virtex 5QV and Virtex 7 FPGA designs
Altera: MAX 5000 and MAX 7000 FPGA designs
Honeywell: HX2000, HX3000, and HX5000 gate array designs
Legacy LSI: 5K, 10K, 20K gate array designs