SOC - Silicon Validation Projects deployed by Faststream

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Silicon Validation

Post-silicon validation is a phase of verification that deals with verification after the real silicon is in place. Tests for post-silicon validation occur on actual devices running at high speeds on commercial, real-world system boards. It is an emerging research topic with several exciting opportunities for innovations in electronic design automation. Although post-silicon validation is a crucial challenge for future systems, very few systematic solutions for this are currently available.

Some of the interesting post-silicon validations deployed by Faststream:

 

Project 01

SOC’s for Cellphone camera, Video Surveillance, HD IP camera, portable Audio.

We emulated numerous SoCs and developed SW applications. It included pre-silicon validation, post-silicon validation, and customer end product application development. We also Pioneered the end-to-end methodology for Pre-Silicon and Post-Silicon validation to achieve first-pass silicon success, complete Software readiness and, accelerate the time to market.

We developed a ROM boot loader, a secondary boot loader, chip level SW packages, a BSP for multiple SOC’s, a starter wire, an SDK, and EVM boards to enable quick customer deployment of the SOC into OEM sockets. We designed a test strategy, methodology, and environment to validate the silicon against, the targeted use case scenarios and design of test benches and test automation setup for regressions and silicon screening.

We created successful strategies, methodologies, and frameworks for the pre-silicon and post-silicon validation with a mix of various tools developed customer-centric prototype applications for DM510, and covered complete HW and SW development for the completed demo/prototype. Included prototypes for the TV viewer, 20MP capture, multi-shot, face detection, smile detection, video stabilization from concept to demo, and optimized for bandwidth performance and power consumption. We resolved critical issues at the SoC design level and board level about power-on and rebooting the performance to improve stability and power consumption of the chip in the end product.

Application and Tools:

Cadence Palladium, Zebu, EVM boards, and starter kits, Portable Audio SOC-DA300, Digital Video and Imaging SOC- DM6446 and DM350, Digital Still Camera SOC- DM320.

 

 

Project 02

ISDB-T One-Seg System software and Components development

We have extensive knowledge of ISDB-T one-seg protocols and system-level design components. So, we set up and configured the HW boards, including the USB interface to the OMAP3630 board, which enabled high-level performance testing.

Application and Tools:

Integration of System Software Components: Tuner, MPEG2 TS parser, H.264, and AAC-LC decoders, DTV Player framework

Hardware: 19nm x2 and x3Flash Memory, Tensilica Diamond 330 HiFi core, ST Microelectronics STi7109, Marvell Switch 88E6063, Tensilica Xtensa LX processor core, RLD I/O, Digital I/O, ADC, DAC, RS-233/422/485 EISA Cards, and Telemetry RF Cards, TI OMAP processor with ARM core. Altera Stratix-V FPGA, RDMA, RoCE

OS/RTOS: Linux, RTOS – Dry-OS (Canon proprietary OS), IRMX-III, OS21 Plus (ST Microelectronics ), Android 4.2, Meego, Moblin

Languages: C, C++, Python

Tools: Xtensa explorer-2.1.1, Xtensa toolchain, Rational Clear case, Cross Compilers, ITP (Intel proprietary), Xt-GDB, Qt-3.0 under Linux, CCS3.1 (Texas Instruments toolchain with explorer for ARM dual-core based processors), VC++, and ST Toolchain, WinCVS. CISCO STB tools (Logger, Image Download client), MS VISIO, MPP. Git, Gerrit, ARM toolchain for Linux.

 

Project 03

DMACM Driver Development

We developed GEMAC, USB, SDIO, DMACM, DMACZ, SDMMC, etc. based on dual Tensilica’s Xtensa LX processor core. We developed system requirement high-level design documents, integration with network applications, and image applications, as well as implemented the execution of system unit and system tests for DMACM IP verification on FPGA. We also implemented the integration test suite for all sub-systems of the SUGH SoC.

The Application

C, RTOS- Dry-OS version 2.3, Xtensa Core, Xtensa toolchain, TEL Dual-Stack IP

February 16, 2022

Semiconductor Design & Verification


Semiconductor Design & Verification
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