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Semiconductor Design & Verification

1. SUBSYSTEM LEVEL VERIFICATION ON ARM PROCESSOR

The Customer:

A renowned wireless communications Company.

The Application:

  • The project is based on the various range of ARM Processor applications such as ARMV7, ARMV8, ARM9, and real-time architecture-based processor subsystems. That is designed to power the multiple switch chips across the performance and application spectrum.
  • From the varying range of Cortex-R5 to Cortex-A53 CPU Cores, and unified communication IPs like PCIe, USB, Ethernet MAC, SPI, JTAG, etc., these subsystems are designed to be strong and flexible while being efficient.

Faststream’s Responsibility:

  • From the ground up, Faststream Technologies worked on the planning and creation of the functional verification infrastructure.
  • Creation and ownership of tests to the neck integration of ARM Debug Interface and processor debug capabilities.
  • We had the ownership of test bench components that verify security architecture.
  • We were involved in Silicon Validation activities using ARM’s RealView Debugger.
  • We helped several teams across the globe of our client to debug their integration issues/chip issues related to this subsystem.
  • Finally, Faststream went through the Verification closure for complex industry-standard protocol IPs like PCIe, USB.

Process:

A Verification team of three engineers worked for fifteen months onsite based.

 

2. FPGA DESIGN AND VERIFICATION OF THE MEASUREMENT UNIT

The Customer:

A Multinational Power Technology Service Company.

Faststream’s Responsibilities:

Design of the measurement unit:

  • Faststream Technologies was involved in designing the measurement units which can measure the voltage and current and connected to the control platform.
  • We designed the RTL code for the FPGA in the voltage and current measurement unit with VHDL using Xilinx Spartan-6 FPGA.
  • Our Design team worked on the design of the Analog to digital converters in the top FPGA file of the measurement units.
  • We designed the port mux for the selection of the backward and forward data from the units in the chain and designed the IIR filter present in the design for filtering the sine wave data and giving it to the communication protocol top file.

Life cycle Management:

  • Our Design team was involved in Code conversion from the old foundation Xilinx design to VHDL code.
  • Faststream was involved in testing the converted FPGA code in the new measurement units present in the test setup.
  • Validated the FPGA .jrd file in Lattice FPGA.
  • We worked on the Testbench creation to check the behavior of the FPGA code and simulation was done using ModelSim.

Verification:

  • Faststream Technologies was involved in the Verification of the FPGA code going into the measurement units.
  • We developed the testbench for the design under test, Testcase writing, VHDL packages, and Test Plan for creation for regression. We used the Modelsim simulator for simulation.
  • We were designing the simulation model for the components on the board and creating the do file for running the simulation.
  • The Debugging part happened in the Modelsim simulation tool and analyzed the simulation output using python script.
  • The Faststream Team interacted with the design and verification team of the Clent.

Model of Engagement:

  • We divided the task in the tenure of 4 weeks iteration, and 5 Engineers were involved in the whole task.
  • The bug reporting was completed by using the Microsoft TFS

3. DIGITAL SYNTHETIC-HETERODYNE DEMODULATION SIGNAL DETECTION ON FPGA BOAR

The Customer

A USA based Telecommunication Company

Description:

The project is based on Digital Synthetic-Heterodyne Demodulation Signal Detection on FPGA Board which is used in the optical signal detection system. It is the custom board contains Spartan 6(XC6SLX150-2FGG484), ADC (AD7760), Anti-aliasing FilterLTC1564, LTC2753 DAC.

Tools Used: Xilinx ISE 14.4, Xilinx System Generator & Verilog HDL

Faststream’s Responsibilities

  • With the help of the FPGA Board and using Verilog HDL, we implemented the Digital Synthetic-Heterodyne Demodulation Technique and created an interface for the ADC (AD7760) in taking the digitized output of 24 bits from it.
  • Mixer data was fed to digital filters named Finite Impulse Response (FIR) filters.
  • Filter samples were fed to other blocks involved in the heterodyne algorithm to detect the message signal.
  • Finally, heterodyne algorithm digital output is given to 16-bit DAC to see detected the phase signal.

4. 8 BIT 1GSPS ANALOG TO DIGITAL CONVERTER (ADC) on TSMC 16 nm

The Customer

A reputed Fabless Semiconductor Company

Environment:

Cadence Virtuoso XL & calibre

Faststream’s Responsibilities

  • Faststream worked on top level integration and few sub blocks such as OTA_adc_stage1, Adc_capdac, Adc_ota_CMFB, switch_matrix, and Comparator.
  • Our Engineers separated differential signals and clock signals from the switch level itself.
  • We did Coaxial shielding for every differential signal and the Offset and INL issues were fixed by exact symmetrical routings. The designers avoided parallel routings of phase signals and differential signals.
  • We worked on common centroid matching for REFCAP. The Clocks were routed very far from the whole REFCAP block because it is very sensitive
  • We placed buffers for long routed RTL nets after extraction results came.

5. RTL DESIGN AND DEVELOPMENT

The Customer

A Fabless Semiconductor Company

Description:

The project is based on RTL Design and development of data acquisition, control, and Signal processing for flow-cytometry-based cell sorting system on the FPGA Board.

Faststream’s Responsibilities:

  • Faststream’s Engineers were involved in Architecture planning, RTL design and verification for data acquisition subsystem with data rates of 60 MBPS, development of FT601 controller for USB3.0 bridge, signal conditioning, and real-time signal processing for feature extraction involving floating-point arithmetic, FPGA process-command, and time-critical control modules.
  • Our Design Team generated static timing analysis reports and constraining design for timing
  • And generated test data, tasks, and golden data for equivalency check and extensive testing/debugging with Python.
  • The Hardware debugging process was completed with Xilinx ILA, Virtual IO. The MATLAB Signal processing algorithm was translated for RTL logic implementation.
October 14, 2021

Silicon Validation


Silicon Validation
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October 14, 2021

SMART FOOD AND BEVERAGES FACTORY


SMART FOOD AND BEVERAGES FACTORY
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