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External Flash Memory Interface IP


Flash memory forms a basic constituent in many FPGA-based embedded systems using Xilinx SRAM-based FPGAs. This is primarily because they store the bitstream file for the FPGA using which the FPGA configures itself at every startup. After configuration, the flash memory is available for user data storage and can be used for non-volatile data storage as long as it is outside of the bitstream area. The External Flash Memory Interface IP designed at Faststream technologies allows accessing these memory locations as a memory-mapped interface and makes the controller agnostic of the underlying SPI interface on which the memory is being interfaced.


Salient features:


  • AXI4-Lite standard user interface. Connects as a 32-bit slave on the AXI interface.
  • Page-wise programming according to the flash memory requirements handled by the IP.
  • Memory single bit error detection and correction implemented in the IP-core.
  • User-configurable, industry-standard NOR flash memories can be interfaced with the IP on SPI and Quad-SPI interfaces.


Block diagram:

External Flash Memory Interface IP