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Flash ADCs are one of the fastest ADCs available which can achieve Giga samples per second conversion rates. One of the limitations of this Improved ADC IP type is that its architectural complexity increases exponentially with an increase in the bit resolution. Hence these are generally available up to 8-bit resolutions. On the contrary, other ADC architectures are slow sampling and are available with high bit resolutions viz. 16-22 bit resolutions. It would be desirable to combine the fast conversion speeds of flash ADCs with high resolutions of SAR and Σ-Δ ADCs.


The Improved ADC IP provides an interface with a flash ADC and supporting components in implementing a multi-step ADC to achieve higher bit resolutions thus integrating the speed of the flash ADC with the resolution of SAR ADC. The controller module in the IP generates all the necessary signals for the ADC and the supporting components to operate in unison. It can be used to double the resolution in bits for any ADC in consideration.


Salient features:


  • The AXI4-Lite standard interface connects as a 32-bit slave on the AXI interface bus.
  • Doubles the nominal flash ADC resolution
  • Programmable sampling rates and ADC interface types to connect multiple types of ADCs and DACs




  • High-resolution requirement analog signals from sensors.


Block Diagram:



Improved ADC IP to implement multi-step ADC