Generation of the clock signal with a fixed but programmable phase difference with respect to a reference input clock is critical in many applications. An all-digital Delay Locked Loop design with several features like a wide lock range for input frequencies, short locking time, and reduced jitter is achieved by this IP. The all-digital nature of the Delay Locked Loop (DLL) design allows the addition of clocking resources in FPGA prototyping of new IPs and for FPGA-based embedded systems using multiple clocking resources. Rigorous simulation has been carried out to evaluate the robustness and performance of the IP. The Delay Locked Loop IP can be used for a variety of applications that require precise phase shifts with respect to reference clocks to adjust for the channel routing delays on the PCB.