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Delay Locked Loop IP


Generation of the clock signal with a fixed but programmable phase difference with respect to a reference input clock is critical in many applications. An all-digital Delay Locked Loop design with several features like a wide lock range for input frequencies, short locking time, and reduced jitter is achieved by this IP. The all-digital nature of the Delay Locked Loop (DLL) design allows the addition of clocking resources in FPGA prototyping of new IPs and for FPGA-based embedded systems using multiple clocking resources. Rigorous simulation has been carried out to evaluate the robustness and performance of the IP. The Delay Locked Loop IP can be used for a variety of applications that require precise phase shifts with respect to reference clocks to adjust for the channel routing delays on the PCB.




  • BIST circuits for measurement of setup and hold times
  • Phase detection and tracking
  • Clock recovery from the input data stream
  • High-speed DDR type interface applications to align data with clock edges


Salient features:


  • Timing resolution:  80ps
  • Operating frequency range:  160MHz – 700 MHz
  • Lock time: 11 cycles
  • Generates user-configurable precise phase shifts from 00 to 3600 with a resolution of 10
  • Delays multiple periodic or aperiodic signals independent of voltage and temperature.

Block diagram:

Delay Locked Loop IP