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AXI-USB 2.0 Device IP


USB is a generic interface in the modern days to connect to various high-speed data peripherals. Many USB device/client controllers are introduced in the embedded systems market, which enables interfacing a host microcontroller to quickly and easily connect to a USB host such as a PC or industrial PC. One of the major limitations of these controllers is the bottleneck on data rate imposed by the interface between the host microcontroller and the USB device controller which more often is a serial UART interface, SPI interface, JTAG interface, or FIFO interface. In FPGA-based embedded systems with reconfiguration capability, it is desirable to implement this USB controller on-chip and thus implement an SoC. Our AXI-USB 2.0 Device IP supports high-speed, high bandwidth isochronous transactions.


We present an AXI-USB 2.0 Device IP to implement on an FPGA in an embedded system. It carries out all tasks like USB device enumeration, endpoint instantiations, etc., and enables bulk, isochronous, interrupts, and control packet transfers over USB. With the addition of a low-cost external USB PHY chip, a USB device can be realized using this IP in no time. The user interface to the host microcontroller instantiated on the FPGA is provided in an AXI interface format and thus, the USB controller is made as a memory-mapped device accessible from the industry-standard AXI bus from the host microcontroller.  


Salient features:


  • AXI4-Lite standard user interface. Connects as a 32-bit slave on the AXI interface.
  • USB serial interface engine implemented to support USB2.0 full speed and high-speed interface.
  • Supports ULPI interface to external PHY chip.
  • Supports control, bulk, interrupt, and isochronous transfers on the USB interface.
  • 8 endpoints instantiated with endpoint 0 as the control endpoint.
  • Handles USB enumeration process.