18-bit Pipeline DSP Slice IP Core

The 18-bit Pipeline DSP slice IP Core provides the best utilization of device resources like memory, I/O, processor, and clock. It is based on the pipelining technique which uses instruction-level parallelism within a single processor. It supports many independent functions, including multiplier, multiplier accumulator (MAC), multiplier-adder, higher bit adder, 3-input adder, barrel shifter, wide bus multiplexers, magnitude comparator, and counter. It also supports connecting multiple DSP slices IP Core to form wide math functions, DSP filters, and complex arithmetic. The architectural highlights of the 18-bit Pipeline DSP slice IP core are as follows:

18-bit by 18-bit, two’s-complement multiplier with the 36-bit result, sign-extended to 48 bits.
Three-input, flexible 48-bit adder/subtractor with optional feedback of accumulator register.
Dynamic user-controlled operation select pins to adapt according to single/multiple slice functions from clock cycle to clock cycle.
Cascading of 18-bit input bus and 48-bit output bus using INTERCONIN/INTERCONOUT pins supporting propagation of partial products from one slice to another.
Multi-precision multiplier and arithmetic support right shifting by 17 bits to obtain wide multiplier partial products.
Symmetric rounding and sequential/parallel support for greater computational accuracy.
Multi-level pipelining options for control and data signals to improve throughput.
MFC(Multi-Functional C-input) supports multiply-add operation, three-input addition, and rounding mode.
Separate reset and clock enable for control and data registers, I/O registers, ensuring maximum clock performance.