July 19, 2023 
Bangalore 
Full Time 
FPGA Designer
Roles & Responsibilities
- Develop the FPGA RTL infrastructure to allow the offload of compute-intensive algorithms onto FPGAs.
- Develop and verify AI/ML-based Intellectual property and Applications.
Skillset
- Big data/DL algorithms, VHDL, Verilog, and SystemVerilog languages.
- Experience with RTL/HLS on FPGA/ASIC
- Linux user and/or kernel-mode development.
- Xilinx , Vivado , Virtex,Kintex, Zynq , Vitis , M
RTL Designer
Skillset
- Experience in implementation of blocks like Digital filters, FFT, IFFT, Memory-IP, USB, USB Subsystem, Ethernet, etc
- FFT, IFFT, Memory-IP, USB, USB Subsystem, Ethernet, etc
- All the regular things like RTL coding, CDC, Linting, basic synthesis, basic STA, etc
- IP level digital RTL development (Verilog/VHDL) (Preferably integration in VHDL and good PCIe knowledge)
- All the regular things like RTL coding, CDC, Linting, basic synthesis, basic STA, etc
- Xilinx , Vivado , Virtex,Kintex, Zynq , Vitis , M
FPGA Designer
Roles & Responsibilities
- Develop the FPGA RTL infrastructure to allow the offload of compute-intensive algorithms onto FPGAs.
- Develop and verify AI/ML-based Intellectual property and Applications.
Skillset
- Big data/DL algorithms, VHDL, Verilog, and SystemVerilog languages.
- Experience with RTL/HLS on FPGA/ASIC
- Linux user and/or kernel-mode development.
- Xilinx , Vivado , Virtex,Kintex, Zynq , Vitis , M
RTL Designer
Skillset
- Experience in implementation of blocks like Digital filters, FFT, IFFT, Memory-IP, USB, USB Subsystem, Ethernet, etc
- FFT, IFFT, Memory-IP, USB, USB Subsystem, Ethernet, etc
- All the regular things like RTL coding, CDC, Linting, basic synthesis, basic STA, etc
- IP level digital RTL development (Verilog/VHDL) (Preferably integration in VHDL and good PCIe knowledge)
- All the regular things like RTL coding, CDC, Linting, basic synthesis, basic STA, etc
- Xilinx , Vivado , Virtex,Kintex, Zynq , Vitis , M