Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floorplanning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
Role involves analyzing DRC, LVS, ERC rule files for industry standard layout verification.
Multiple Power Domain Analysis using standard Power Formats UPF/CPF
Experience in ASIC Physical Design RTL to GDSII Implementation flow.
Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc.
Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal)