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RTLDESIGN

Faststream‘s RTL design engineers have in-depth experience in various aspects of the RTL design flow on chips used in the networking, processors, multimedia, mobile and automotive industries.

 

Our team possesses how to balance current design techniques with standard IPs and with varying experience ranging from 2 to 10 years on designs going up to multi-million gates. As a result, Faststream Technologies earned a reputation in the Semiconductor Industry as the leading RTL design services provider for highly complex designs.

Our Design Engineers coordinate with the architecture team to define micro-architectures for various blocks of DSP core and develop RTL for multiple logic blocks of a DSP core and sub-system for SoC integration. It can run in several frontend tools to check for linting, clock domain crossing. The RTL Design Engineers work with the physical design team on design constraints and timing closure, work with the low power team on power optimization and coordinate with the verification team to collaborate on test plan, coverage plan, and coverage closure.

OUR RTL DESIGN EXPERTISE 

 

  • IP/SoC Design and Verification
  • Microarchitecture development
  • Using different verification methodologies like eRM/OVM/UVM to develop an extendable test-bench/test-cases environment
  • Execution of detailed verification plan from spec and working with designers, system engineers, and architects
  • Development of verification testbench components for chip/module level using Verilog/System Verilog/C/C++
  • Development of BFMs, Monitors, Checkers Blocks level, Sub-system level, and SoC-level verification and Test Bench Development

  • Simulation systems (e.g. Modelsim, VCS)
  • Static timing tools (e.g. Prime Time)
  • Synthesis tools (e.g. Design Compiler, Physical )
  • RTL-to-GDSII using Cadence tool

The RTL Signoff could be a series of well-defined necessities that have to be met throughout the RTL phase of IC design and verification before moving on to the succeeding phase. The succeeding phase is often synthesis, followed by place & route. The justification for RTL Signoff is to create positives that the correct verification, checks, and fixes, are performed on the RTL, immediately within the flow, instead of waiting till they’re found throughout the later stages, leading to pricey retread.

 

Examples of RTL Signoff requirements include:

 

  • Verification of Structural Design Codes which includes false and multi-cycle paths.
  • Code and functional coverage with assertions level verification.
  • Linting for simulation and synthesis.
  • Through static and dynamic verification, verification of Clock and Reset domain.
  • Meeting the power goal which includes power estimation and reduction.
  • Verification of Voltage and Power Domain.
  • Unified Power Format(UPF) verification.
  • Inspection of Area, timing, and congestion for ensuring the physical clean RTL

Overview

 

Faststream Technologies allows designers and DFT experts to catch “test-related” issues early in the design cycle, at RTL. It also allows the exploration of different DFT implementation options such as test points and estimates the impact on the design implementation steps. Faststream Technologies helps make the right choices when it comes to DFT which saves time, effort as well as cost.

 

Key Features

 

  • Absolute Rule Checks for DFT Design.
  • Can be entitled to running 3rd party ATPG at RTL.
  • Enhancement capabilities for following Test Coverage.
    • Clock / Reset controllability auto-fix.
    • Shadow logic insertion.
    • X generator analysis.
    • Test point insertion.
  • Specific ATPG aware test coverage evaluation.
  • Automated flow for compression exploration.
  • Support Unified Power Format-based checks at RTL.
  • Graphical User Interface.
    • Identify the root cause of DFT violations.
    • Test topology for low coverage debug.
  • Hierarchical DFT exploration based on Core Test Language (CTL) models.
  • Capability to create RTL with scan / Auto-fix logic

As most IP is sourced as RTL, signoff checks may be enforced as a part of hands-on necessities from the  IP provider, and as acceptance checks by the SoC integration team. When addressing configurable IP, there’s no guarantee the configuration during which a designer needs to use the IP within the SoC has been completely valid by the provider.

At the SoC level, the integrator must validate expectations in the IP and make necessary adjustments when the two are not in sync. After validating, the SoC-level signoff can focus on IP integration and commonplace issues at this higher level.

 

Extra Advantages with SoC Signoff:

 

  • In IP Signoff, it’s not necessary to validate the inner part of IP at the SoC integration stage, as long as the IP validation model is showing intelligence abstracted.
  • Abstraction will drive associate degree order of magnitude improvement in analysis time whereas reducing computing hardware needs.
  • Finally, this ends up in a considerably simplified flow.

RTL Design Services