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Faststream Technologies RTCA DO-254 Verification services, “Design Assurance Guidance for Airborne Electronic Hardware” is currently recognized by the FAA via FAA AC 20-152 as a means of compliance and guidance for the design assurance of complex electronic hardware such as FPGAs, Pcie, PLDs, and ASICs in airborne systems.







Faststream Technologies RTCA DO-254 Verification services, “Design Assurance Guidance for Airborne Electronic Hardware” is currently recognized by the FAA via FAA AC 20-152 as a means of compliance and guidance for the design assurance of complex electronic hardware such as FPGAs, Pcie, PLDs, and ASICs in airborne systems.


The Challenges in Hardware Verification


Functional verification of digital designs in real hardware has been a serious undertaking when designing under the DO-254 standard. Chapter 6.2 Verification Process of DO-254 species that requirements must be preserved and verified from the RTL simulation stage to the hardware verification stage. In doing this, designers are presented with significant challenges for DO-254 Verification services such as:



  • Limited controllability and visibility of FPGA I/Os.
  • Ensuring RTL simulation and hardware testing results match.
  • Development of test vectors to cover all design requirements.
  • Results capturing and documentation
  • Lack of automation in the verification cycle


The Solution


FaststreamTech’s DO-254/CTS is a certifiable at-speed in-target testing environment for Level A/B complex designs and is dedicated to addressing the stringent guidelines of the DO-254 Chapter 6.2 Verification Process.  DO-254/CTS consists of a fully customized hardware and software package designed to replay RTL simulation during hardware testing without any changes to the DUT and testbench.  It provides a single and automated environment to test all FPGA level requirements ideal for DO-254 hardware verification.



  • At-Speed Design Verification in Target Devices.
  • Automatic Test Vector Generation for Target Devices.
  • Auto-Capture and Analysis of results at all Design Stages.
  • Easy Design Requirements Traceability.
  • Independent EDA Tool Assessment.
  • Significantly shortens Device Verification Time



  • COTS Motherboard- PCIe-PCIe Interface
  • Custom Daughter Board
  • Custom Software Package

KEY BENEFITS of DO-254 Verification services

PCIe Level In-Hardware Verification:

In compliance with the document FAA AC 20-152, verification at the PCIelevel must be done to ensure completeness of testing.  PCIe level verification is performed before system-level verification.  All FPGA level requirements verified using DO-254/CTS do not have to be verified again at the system level per RTCA/DO-254 specification.

Running at Required Operational Speed in excess of 250 MHz

Allows streaming of test vectors through the FPGA inputs at the required operational speed using real clocks in excess of  250 MHz. If the required simulation time is 500ms, then hardware testing completes within 500ms.  Additional features to vary the frequency and voltage to +-10% can also be used for robustness.

Automatic Generation of Test Vectors for Hardware Testing

Development of test vectors for hardware testing for an average Level A/B design normally takes 6-12 months of manual engineering time.  DO-254/CTS is equipped with a utility that converts the test bench within minutes into test vectors to be used for hardware testing.

Hardware Testing Results Visualization with Waveform Viewer

Allows capturing and visualization of results using the simulator’s standard waveform viewer, providing storage for waveform files of up to 16TB and capturing of results immediately after simulation.

Single-Environment to Verify all FPGA Level Requirements

It consists of custom hardware with a PCIe interface and software providing a single-environment to test all FPGA level requirements, specifically designed to avoid manual bypasses of cables and wires which are typically prone to errors and bugs.

Automated In-Hardware Testing

DO-254/CTS is a “push-button” automated in-hardware testing environment to test all FPGA level requirements.  It is equipped with a utility to automatically compare RTL simulation results with hardware testing results.  The utility displays either a PASS or FAIL message in which results can be further investigated using a standard waveform viewer.

Target Device Testing

The design must be tested in the target device per RTCA/DO-254 specification sections 1.1 and 6.3.1.  DO-254/CTS consists of a custom daughterboard that contains the specific family/package or part number of the FPGA/PLD device. From vendors such as Altera, Lattice, Microsemi (Actel), and Xilinx.




Faststream Technologies is implementing an automated method to measure RTL to a company standard that improves overall productivity by eliminating variability in design code quality. For example, defining a weighted set of linter rules that the designer can run at any time during RTL development augments manual code inspections within the assurance process. In turn, this process presents a documented method for RTL code validation that increases the DER’s confidence level for DO-254 approval.
Importantly, there is no need to alter any of the test vectors as doing so would break traceability with the RTL test bench, as derived from the original requirements. Indeed, DO-254 certification relies on information gathered from the project conception, planning, design creation, implementation, and testing stages; and states that the requirements validated during RTL simulation must be validated again during hardware verification.

Design Documentation



Design verification is the cornerstone of our commitment to producing a quality product. Designs continue to grow in functionality at an incredible rate, and verification of these designs can no longer be performed through standard techniques such as directed vector tests. The number of possible states in a given design can well exceed the number of atoms in the universe. This gives rise to the challenges of implementing an effective verification methodology to ensure that the design has been completely verified for every possible state that it might find itself in. Verification also needs to uncover corner cases such as unintentional “sneak paths” for enabling or disabling critical systems. In short, the company must present a process that proves design verification is complete. The only way to approach this requirement is to employ Advanced Verification Methodology (AVM).




As defined in the DO-254 standard, an artifact is any document, report, or result that is created or produced as part of the FPGA or ASIC design process. Faststream’s design process progressively transforms a written requirement document through the creation of RTL code and ultimately to a programming bitstream or a GDS II file. The quantity of design documentation, or artifacts, produced by this process is typically large. In addition, DO-254 requires the creation of several mandatory documents in support of the standard. Teams constantly review artifacts, and DERs examine the documents and design review results.

DO-254 Verification