Design Verification

We provide ASIC and FPGA functional verification services spanning the entire coverage-driven verification flow from specification to coverage sign-off. We have extensive experience in all major hardware verification languages (HVLS) such as e-Language and SystemVerilog, and methodologies such as UVM, OVM, VMM, and eRM.

We are proficient in the use of all major EDA vendor tools, such as Cadence Incisive® Enterprise Simulator, the Synopsys VCS® functional verification solution, and Mentor’s Questa® Advanced Simulator. We also use the Cadence® Palladium® series of accelerators/emulators, system-level modeling languages such as SystemC, and tools like MATLAB®.

System-Level Verification, the planning, and implementation of the verification process need to be done carefully due to the very high clock cycle consumption. The verification process requires in-depth planning, advanced verification skills like object-oriented language programming (SystemVerilog, C++/SystemC), and methodology awareness (UVM), as well as a creative approach to problem-solving.

We have the expertise to provide system-level verification services for complex SoCs, involving working with various hardware and software IPs and using specific tools like hardware acceleration and hardware emulation.