ASIC, FPGA, SoC Top Level Verification

Verification is always a major challenge in your project, ensuring that your design is bug-free within the given time constraints. FaststreamTech provides its customers with the Top Level Verification approach to every complex technical stop. With the ever-increasing size of ASIC and FPGA, the complexity of verification is increasing exponentially. Each small change in configuration is bringing about long verification. Subsequently, 50-70% of chip development resources are currently getting devoured by verification efforts. With the processor now part of SoC, the complexity of verification further increases. Our team has broad involvement in taking up full responsibility or being part of a larger customer team, delivering module to full-chip verification for complex chips. We have worked with a simple verification environment created using simple Verilog or VHDL to full coverage driven random environment in System Verilog using UVM. Our team has developed reusable Verification components without any preparation and also utilized industry-standard VIPs as a major aspect of condition to lessen the time and enhance the nature of the check. We have verified various chips, pre, and post-silicon, to ensure the highest quality working chips.

Verification Services

Verification Capabilities

Verification planning, feature extraction, capturing functional coverage, and checkpoints
Metric drove verification techniques using advanced tools to increase the verification confidence
Formal verification techniques
Creation of wrappers and multi-language interface sockets
Regression management
Register abstraction based flow enabling design and verification reuse
End-to-end verification closure from specification to RTL signoff

Verification Planning and Strategy

Specification review – identifying the key features/modules to be verified and the most appropriate approach for each one
HW / SW co-verification techniques
Availability of in-house ‘legacy’ verification techniques/knowledge
Recommendations on the choice of EDA tools and flows
Consideration for module, sub-system, and chip-level verification
Resources, schedule, costs to implement the verification strategy
Possible use of in-house or 3rd-party Verification IP (VIP)

Verification Flow

Planning Phase: The specification is reviewed and a verification plan document generated. The verification plan captures the required features that must be checked by the verification activities (RTL functional verification, FPGA prototyping, emulation, formal techniques, etc).
The focus here is on the creation of a working test environment.
The test environment is completely coded including cover points, checkers, and assertions.
During this phase, the remaining coverage holes are tackled and bug fixes implemented

OUR TOP LEVEL VERIFICATION APPROACH

Advanced ASIC Verification:

Top Level Verification approach by Faststream is an exhaustive scope of ASIC verification services to help our clients to accomplish working silicon the first time around. Verification represents one of the biggest challenges confronting IC developers getting their design into the market inside acceptable timescales. Silicon technology continues to advance giving increasing scope to incorporate an extensive variety of IP including digital/analog cells, embedded processors, memories, high-speed IO, in-house/3rd party IP, and so on onto a single device. Traditional verification techniques (e.g. directed testing) basically can’t adapt to this complexity. We comprehend the difficulties introduced by these designs and work with our customers to give everything from in-depth knowledge to solve a specific verification problem, to delivering a comprehensive verification solution for a complete chip.

Digital ASIC/SoC Design and Verification:

Our design and verification offerings under the digital ASIC/SoC Design and verification portfolio envelopes:

Synthesizable IPs (RTL) for digital functional blocks including high-speed DSP functional block sets
Synthesizable IO protocols
Memory and Microcontroller Interface Protocols
High-Speed Arithmetic Functions
Verification IPs for an assortment of functional blocks and IPs
Design support for Physical Design and Verification
Complete Chip Integration

FPGA Verification Services

Pre-Study and Specification

•Determination definition in collaboration with the customer
•FPGA determination
•Cost assessment
•IP selection

Implementation

•Automated synthesis & mapping flow
•Constraints definition and timing closure

On-board Validation

•FPGA debugging using probing, debug modules
•Advanced verification flow using same test scenarios as in simulation with communication through JTAG, PCIe, Ethernet
•Automated flow

Design and Verification

•Architecture definition
•RTL coding
•Linting verification as per the set of coding rules
•Broad simulation at the module and top-level
• Nonregression testing