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Digital Up Conversion (DUC)


An interpolating filter chain, a numerically controlled oscillator (NCO), and a mixer comprise the Digital Up Conversion (DUC). The filter chain consists of a low-pass interpolator, a half-band interpolator, a CIC compensation interpolator (FIR), a CIC interpolator, and CIC gain correction.

The first low-pass interpolator achieves the precise Fpass and Fstop features of the DUC. A half-band filter is a form of the middle-of-the-road interpolator. Because sample rates are lower at the beginning of the chain, the earlier filters can maximize resource use by sharing multipliers. The CIC compensation interpolator improves the spectral response by accounting for later CIC droop when interpolating by two. The CIC interpolator has a high interpolation factor that is enough for filter chain upsampling.

The DUC’s input interpolation factor is 2 and a decimation factor of 256 to achieve an output sample rate of 270.83 kHz. For cell search and master information block (MIB) recovery, LTE receivers typically employ a sampling rate of 1.92 Msps. The Digital Upconverter filters are specifically built for this use. The DUC has been designed to operate at a clock rate of 122.88 MHz.

DUC Block-Diagram of 5G Base Staion

 Conversion Features and Process:


  • 70 MHz IF, 2.5.8, & 22MHz BWs (3dB)
  • 204.8 MHz DAC Sample Rate
  • The modem provides a 25 kHz fine-tune step
  • Receiver / Exciter minimum freq step = 0.5 MHz, settling time < 100 us to 100Hz

Digital up conversion in 5G

  • Basebang samples are converted to 70 MHz “digital IF”
  • The Polyphase filter approach reduces the required 204.8 Msps processing to the simple data transfer
  • 208.8 Msps DAC sample rate required to reduce DAC sinx/x roll-off
  • The final 2x interpolation process employs parallel FIR filters that process at a 1x rate
  • As a result of the quarter-wave frequency shift, the number of filter taps is reduced by a factor of two
  • Maintain 16 bits in/out of DDC
  • Complex mixer functions should keep 18 bits at the input and truncate to 16 bits at the output
  • Digital Upconverter shares a single DDS FPGA instantiation
  • DUC shares the same FPGA filter structures